From 8315f5f3ea43150d250aa16575ab274913f93d2a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 6 Nov 2022 19:55:54 -0600 Subject: Add PSR control signal set --- rtl/core/control/stall.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'rtl/core/control/stall.sv') diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv index 5ac1c7a..edf9265 100644 --- a/rtl/core/control/stall.sv +++ b/rtl/core/control/stall.sv @@ -5,6 +5,7 @@ module core_control_stall input logic clk, input datapath_decode dec, + input psr_decode dec_psr, input data_decode dec_data, input snd_decode dec_snd, @@ -32,7 +33,7 @@ module core_control_stall assign rn_hazard = dec_data.uses_rn && (final_rd == dec_data.rn || dec_data.rn == `R15); assign snd_hazard = !dec_snd.is_imm && (dec_snd.r == final_rd || dec_snd.r == `R15); - assign flags_dependency = dec.update_flags || dec.conditional; + assign flags_dependency = dec_psr.update_flags || dec.conditional; assign updating_flags = final_update_flags || update_flags; always_ff @(posedge clk) -- cgit v1.2.3