From 6cb000adf57d7af2ec4aac8fd93d12f09cc63556 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 12 Nov 2022 21:47:54 -0600 Subject: Implement CPU halt --- rtl/core/control/stall.sv | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'rtl/core/control/stall.sv') diff --git a/rtl/core/control/stall.sv b/rtl/core/control/stall.sv index 6d2b4e2..c2a6ddd 100644 --- a/rtl/core/control/stall.sv +++ b/rtl/core/control/stall.sv @@ -4,6 +4,7 @@ module core_control_stall ( input logic clk, rst_n, + halt, input insn_decode dec, @@ -14,7 +15,8 @@ module core_control_stall writeback, input reg_num final_rd, - output logic stall, + output logic halted, + stall, bubble, next_bubble ); @@ -22,7 +24,8 @@ module core_control_stall logic pc_rd_hazard, pc_wr_hazard, rn_pc_hazard, snd_pc_hazard, flags_hazard, flags_dependency, updating_flags; - assign stall = next_cycle != ISSUE || next_bubble; + assign stall = next_cycle != ISSUE || next_bubble || halt; + assign halted = halt && !next_bubble; assign next_bubble = pc_rd_hazard || pc_wr_hazard || flags_hazard; //FIXME: pc_rd_hazard no debería definirse sin final_writeback? -- cgit v1.2.3