From d6fff0eb1ce867192d30babb839fc09c30049f0b Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 7 Dec 2022 20:59:22 -0600
Subject: Fix register-indirect shifts

---
 rtl/core/control/select.sv | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'rtl/core/control/select.sv')

diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 1ea2c31..0ab7bb2 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -29,7 +29,9 @@ module core_control_select
 		if(next_cycle.issue) begin
 			ra = dec.data.rn;
 			rb = dec.snd.r;
-		end else if(next_cycle.transfer) begin
+		end else if(next_cycle.rd_indirect_shift)
+			rb = r_shift;
+		else if(next_cycle.transfer) begin
 			if(ldst_next)
 				// final_rd viene de dec.ldst.rd
 				rb = pop_valid ? popped : final_rd;
-- 
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