From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 9 Nov 2022 09:25:48 -0600
Subject: Implement reset

---
 rtl/core/control/select.sv | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

(limited to 'rtl/core/control/select.sv')

diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
index 09fb144..80a437f 100644
--- a/rtl/core/control/select.sv
+++ b/rtl/core/control/select.sv
@@ -3,6 +3,7 @@
 module core_control_select
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 
@@ -46,18 +47,17 @@ module core_control_select
 		endcase
 	end
 
-	always_ff @(posedge clk) begin
-		last_ra <= ra;
-		last_rb <= rb;
-
-		if(next_cycle == ISSUE)
-			r_shift <= dec.snd.r_shift;
-	end
-
-	initial begin
-		last_ra = {$bits(ra){1'b0}};
-		last_rb = {$bits(rb){1'b0}};
-		r_shift = {$bits(r_shift){1'b0}};
-	end
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			last_ra <= {$bits(ra){1'b0}};
+			last_rb <= {$bits(rb){1'b0}};
+			r_shift <= {$bits(r_shift){1'b0}};
+		end else begin
+			last_ra <= ra;
+			last_rb <= rb;
+
+			if(next_cycle == ISSUE)
+				r_shift <= dec.snd.r_shift;
+		end
 
 endmodule
-- 
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