From 2c49f7b342d393b95372bc29708629f397d2d185 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 6 Nov 2022 15:32:07 -0600
Subject: Split regfile read select logic out of control.sv

---
 rtl/core/control/select.sv | 48 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 rtl/core/control/select.sv

(limited to 'rtl/core/control/select.sv')

diff --git a/rtl/core/control/select.sv b/rtl/core/control/select.sv
new file mode 100644
index 0000000..a073e24
--- /dev/null
+++ b/rtl/core/control/select.sv
@@ -0,0 +1,48 @@
+`include "core/uarch.sv"
+
+module core_control_select
+(
+	input  logic       clk,
+
+	input  data_decode dec_data,
+	input  snd_decode  dec_snd,
+
+	input  ctrl_cycle  cycle,
+	                   next_cycle,
+	input  logic       issue,
+	                   mem_ready,
+	                   pop_valid,
+	input  reg_num     popped,
+	                   final_rd,
+
+	output reg_num     ra,
+	                   rb
+);
+
+	reg_num r_shift;
+
+	always_ff @(posedge clk)
+		unique0 case(next_cycle)
+			ISSUE:
+				if(issue) begin
+					ra <= dec_data.rn;
+					rb <= dec_snd.r;
+					r_shift <= dec_snd.r_shift;
+				end
+
+			RD_INDIRECT_SHIFT:
+				rb <= r_shift;
+
+			TRANSFER:
+				if(cycle != TRANSFER || mem_ready)
+					// final_rd viene de dec_ldst.rd
+					rb <= pop_valid ? popped : final_rd;
+		endcase
+
+	initial begin
+		ra = {$bits(ra){1'b0}};
+		rb = {$bits(rb){1'b0}};
+		r_shift = {$bits(r_shift){1'b0}};
+	end
+
+endmodule
-- 
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