From 2864ed33089d43a898928095de01eefecaf448e4 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 24 Oct 2022 07:48:07 -0600
Subject: Split mux logic out of control.sv

---
 rtl/core/control/mux.sv | 50 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100644 rtl/core/control/mux.sv

(limited to 'rtl/core/control/mux.sv')

diff --git a/rtl/core/control/mux.sv b/rtl/core/control/mux.sv
new file mode 100644
index 0000000..58d2197
--- /dev/null
+++ b/rtl/core/control/mux.sv
@@ -0,0 +1,50 @@
+`include "core/uarch.sv"
+
+module core_control_mux
+(
+	input  logic       clk,
+
+	input  word        rd_value_a,
+	                   rd_value_b,
+
+	input  ctrl_cycle  cycle,
+	input  logic       data_snd_is_imm,
+	input  logic[5:0]  data_shift_imm,
+	input  logic[11:0] data_imm,
+	input  ptr         pc,
+	input  word        saved_base,
+	                   mem_offset,
+
+	output word        alu_a,
+	                   alu_b,
+	output logic[7:0]  shifter_shift
+);
+
+	always_comb begin
+		unique case(cycle)
+			RD_INDIRECT_SHIFT: shifter_shift = rd_value_b[7:0];
+			default:           shifter_shift = {2'b00, data_shift_imm};
+		endcase
+
+		unique case(cycle)
+			TRANSFER:  alu_a = saved_base;
+			EXCEPTION: alu_a = {pc, 2'b00};
+			default:   alu_a = rd_value_a;
+		endcase
+
+		unique case(cycle)
+			RD_INDIRECT_SHIFT, WITH_SHIFT:
+				alu_b = saved_base;
+
+			TRANSFER:
+				alu_b = mem_offset;
+
+			default:
+				if(data_snd_is_imm)
+					alu_b = {{20{1'b0}}, data_imm};
+				else
+					alu_b = rd_value_b;
+		endcase
+	end
+
+endmodule
-- 
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