From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 9 Nov 2022 09:25:48 -0600
Subject: Implement reset

---
 rtl/core/control/mul.sv | 64 ++++++++++++++++++++++++-------------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

(limited to 'rtl/core/control/mul.sv')

diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
index 8f7cd91..9e66053 100644
--- a/rtl/core/control/mul.sv
+++ b/rtl/core/control/mul.sv
@@ -3,6 +3,7 @@
 module core_control_mul
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 	input  logic       mul_ready,
@@ -31,42 +32,41 @@ module core_control_mul
 	assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b};
 	assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b};
 
-	always_ff @(posedge clk) begin
-		mul_start <= 0;
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			mul <= 0;
+			mul_add <= 0;
+			mul_long <= 0;
+			mul_start <= 0;
+			mul_signed <= 0;
+			mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}};
+			mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}};
 
-		unique case(next_cycle)
-			ISSUE: begin
-				mul <= issue && dec.ctrl.mul;
-				mul_add <= dec.mul.add;
-				mul_long <= dec.mul.long_mul;
-				mul_signed <= dec.mul.signed_mul;
-				mul_r_add_hi <= dec.mul.r_add_hi;
-				mul_r_add_lo <= dec.mul.r_add_lo;
-			end
+			hold_a <= 0;
+			hold_b <= 0;
+		end else begin
+			mul_start <= 0;
 
-			MUL:
-				mul_start <= cycle != MUL;
+			unique case(next_cycle)
+				ISSUE: begin
+					mul <= issue && dec.ctrl.mul;
+					mul_add <= dec.mul.add;
+					mul_long <= dec.mul.long_mul;
+					mul_signed <= dec.mul.signed_mul;
+					mul_r_add_hi <= dec.mul.r_add_hi;
+					mul_r_add_lo <= dec.mul.r_add_lo;
+				end
 
-			MUL_ACC_LD: begin
-				hold_a <= rd_value_a;
-				hold_b <= rd_value_b;
-			end
-		endcase
-	end
+				MUL:
+					mul_start <= cycle != MUL;
 
-	//TODO: mul update_flags
-
-	initial begin
-		mul = 0;
-		mul_add = 0;
-		mul_long = 0;
-		mul_start = 0;
-		mul_signed = 0;
-		mul_r_add_hi = {$bits(mul_r_add_hi){1'b0}};
-		mul_r_add_lo = {$bits(mul_r_add_lo){1'b0}};
+				MUL_ACC_LD: begin
+					hold_a <= rd_value_a;
+					hold_b <= rd_value_b;
+				end
+			endcase
+		end
 
-		hold_a = 0;
-		hold_b = 0;
-	end
+	//TODO: mul update_flags
 
 endmodule
-- 
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