From 4ccb96c1aaf348f677954171751b58ad8f4dccf1 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 7 Nov 2022 19:07:55 -0600 Subject: Remove false dependencies on control.issue (long combinational) --- rtl/core/control/mul.sv | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) (limited to 'rtl/core/control/mul.sv') diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv index c3625f8..5377045 100644 --- a/rtl/core/control/mul.sv +++ b/rtl/core/control/mul.sv @@ -36,15 +36,14 @@ module core_control_mul mul_start <= 0; unique case(next_cycle) - ISSUE: - if(issue) begin - mul <= dec.mul; - mul_add <= dec_mul.add; - mul_long <= dec_mul.long_mul; - mul_signed <= dec_mul.signed_mul; - mul_r_add_hi <= dec_mul.r_add_hi; - mul_r_add_lo <= dec_mul.r_add_lo; - end + ISSUE: begin + mul <= issue && dec.mul; + mul_add <= dec_mul.add; + mul_long <= dec_mul.long_mul; + mul_signed <= dec_mul.signed_mul; + mul_r_add_hi <= dec_mul.r_add_hi; + mul_r_add_lo <= dec_mul.r_add_lo; + end MUL: mul_start <= cycle != MUL; -- cgit v1.2.3