From 8ab171864291c74d0a22cac911bc8a8aee8a7d5b Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 15 Nov 2022 21:48:08 -0600
Subject: Fix false undefined exception

---
 rtl/core/control/issue.sv | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'rtl/core/control/issue.sv')

diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv
index c1c932e..d124a0d 100644
--- a/rtl/core/control/issue.sv
+++ b/rtl/core/control/issue.sv
@@ -32,11 +32,13 @@ module core_control_issue
 			undefined <= 0;
 			pc_visible <= 2;
 		end else if(next_cycle.issue) begin
-			undefined <= dec.ctrl.undefined;
+			if(issue) begin
+				undefined <= dec.ctrl.undefined;
 
 `ifdef VERILATOR
-			if(dec.ctrl.undefined)
-				$display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn);
+				if(dec.ctrl.undefined)
+					$display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn);
+			end
 `endif
 
 			pc <= insn_pc;
-- 
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