From 79e05aa7f0ccce6eb26248ddef3e928727857a9c Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 11 Dec 2022 23:54:38 -0600 Subject: Implement prefetch aborts --- rtl/core/control/issue.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) (limited to 'rtl/core/control/issue.sv') diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index ffdf250..23ecdcf 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -8,6 +8,7 @@ module core_control_issue input insn_decode dec, input ptr insn_pc, + input logic issue_abort, input ctrl_cycle next_cycle, input logic next_bubble, @@ -18,6 +19,7 @@ module core_control_issue output logic issue, undefined, + prefetch_abort, output ptr pc, pc_visible, next_pc_visible @@ -34,12 +36,14 @@ module core_control_issue pc <= 0; undefined <= 0; pc_visible <= 2; + prefetch_abort <= 0; end else if(next_cycle.issue) begin if(valid) begin undefined <= dec.ctrl.undefined; + prefetch_abort <= issue_abort; `ifdef VERILATOR - if(dec.ctrl.undefined) + if(dec.ctrl.undefined && !issue_abort) $display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn); `endif end -- cgit v1.2.3