From a055bc85bc50897644e7ed62699abff46d818d5f Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 15 Nov 2022 18:32:55 -0600 Subject: Rewrite duplicate ldst logic as signal ldst_next --- rtl/core/control/data.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'rtl/core/control/data.sv') diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv index 049cf0e..6a7ec15 100644 --- a/rtl/core/control/data.sv +++ b/rtl/core/control/data.sv @@ -16,6 +16,7 @@ module core_control_data input ctrl_cycle cycle, next_cycle, input ptr pc, + input logic ldst_next, input word mem_offset, input psr_flags flags, @@ -89,7 +90,7 @@ module core_control_data c_in <= c_shifter; saved_base <= q_shifter; end else if(next_cycle.transfer) begin - if(!cycle.transfer || mem_ready) + if(ldst_next) saved_base <= q_alu; end else if(next_cycle.exception) begin alu <= `ALU_ADD; -- cgit v1.2.3