From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 9 Nov 2022 09:25:48 -0600 Subject: Implement reset --- rtl/core/control/data.sv | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) (limited to 'rtl/core/control/data.sv') diff --git a/rtl/core/control/data.sv b/rtl/core/control/data.sv index 0d87b02..fc936dc 100644 --- a/rtl/core/control/data.sv +++ b/rtl/core/control/data.sv @@ -3,6 +3,7 @@ module core_control_data ( input logic clk, + rst_n, input insn_decode dec, input word rd_value_a, @@ -62,8 +63,16 @@ module core_control_data endcase end - always_ff @(posedge clk) - unique case(next_cycle) + always_ff @(posedge clk or negedge rst_n) + if(!rst_n) begin + alu <= {$bits(alu){1'b0}}; + c_in <= 0; + shifter <= {$bits(shifter){1'b0}}; + data_imm <= {$bits(data_imm){1'b0}}; + data_shift_imm <= {$bits(data_shift_imm){1'b0}}; + data_snd_is_imm <= 0; + data_snd_shift_by_reg <= 0; + end else unique case(next_cycle) ISSUE: begin alu <= dec.data.op; c_in <= flags.c; @@ -100,14 +109,4 @@ module core_control_data end endcase - initial begin - alu = {$bits(alu){1'b0}}; - c_in = 0; - shifter = {$bits(shifter){1'b0}}; - data_imm = {$bits(data_imm){1'b0}}; - data_shift_imm = {$bits(data_shift_imm){1'b0}}; - data_snd_is_imm = 0; - data_snd_shift_by_reg = 0; - end - endmodule -- cgit v1.2.3