From d9dfa098323bc9ffdc9e976bd4106efc75b2954a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 15 Nov 2022 23:18:09 -0600 Subject: Implemente byte-enable signal in stores --- rtl/core/control/control.sv | 1 + 1 file changed, 1 insertion(+) (limited to 'rtl/core/control/control.sv') diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index adfe9f7..4bff86e 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -47,6 +47,7 @@ module core_control output logic[7:0] shifter_shift, output ptr mem_addr, output word mem_data_wr, + output logic[3:0] mem_data_be, output logic mem_start, mem_write, output word mul_a, -- cgit v1.2.3