From 8315f5f3ea43150d250aa16575ab274913f93d2a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 6 Nov 2022 19:55:54 -0600 Subject: Add PSR control signal set --- rtl/core/control/control.sv | 1 + 1 file changed, 1 insertion(+) (limited to 'rtl/core/control/control.sv') diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 056606d..917dbf8 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -4,6 +4,7 @@ module core_control ( input logic clk, input datapath_decode dec, + input psr_decode dec_psr, input branch_decode dec_branch, input data_decode dec_data, input snd_decode dec_snd, -- cgit v1.2.3