From 6b163a88179ac3073d22622be4991f332529c8bd Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sat, 10 Dec 2022 19:56:19 -0600
Subject: Expose cp15 signals to core toplevel

---
 rtl/core/control/control.sv | 1 +
 1 file changed, 1 insertion(+)

(limited to 'rtl/core/control/control.sv')

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 79d6d36..3c55507 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -25,6 +25,7 @@ module core_control
 	input  word            mul_q_hi,
 	                       mul_q_lo,
 	                       coproc_read,
+	input  logic           high_vectors,
 
 `ifdef VERILATOR
 	input  word            insn,
-- 
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