From 46eae9622ab6f1a39c6253dc0998e03c57513510 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 18 Dec 2022 13:19:55 -0600
Subject: Implement mode-translated memory accesses

---
 rtl/core/control/control.sv | 1 +
 1 file changed, 1 insertion(+)

(limited to 'rtl/core/control/control.sv')

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index a421572..cab47ce 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -61,6 +61,7 @@ module core_control
 	output logic[3:0]      mem_data_be,
 	output logic           mem_start,
 	                       mem_write,
+	                       mem_user,
 	output word            mul_a,
 	                       mul_b,
 	                       mul_c_hi,
-- 
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