From 2864ed33089d43a898928095de01eefecaf448e4 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 24 Oct 2022 07:48:07 -0600
Subject: Split mux logic out of control.sv

---
 rtl/core/control/control.sv | 31 +++++--------------------------
 1 file changed, 5 insertions(+), 26 deletions(-)

(limited to 'rtl/core/control/control.sv')

diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv
index 2c5c6f1..059cb2d 100644
--- a/rtl/core/control/control.sv
+++ b/rtl/core/control/control.sv
@@ -89,34 +89,13 @@ module core_control
 		.pop_lower(popped_lower)
 	);
 
-	always_comb begin
-		unique case(cycle)
-			RD_INDIRECT_SHIFT: shifter_shift = rd_value_b[7:0];
-			default:           shifter_shift = {2'b00, data_shift_imm};
-		endcase
-
-		unique case(cycle)
-			TRANSFER:  alu_a = saved_base;
-			EXCEPTION: alu_a = {pc, 2'b00};
-			default:   alu_a = rd_value_a;
-		endcase
-
-		unique case(cycle)
-			RD_INDIRECT_SHIFT, WITH_SHIFT:
-				alu_b = saved_base;
-
-			TRANSFER:
-				alu_b = mem_offset;
-
-			default:
-				if(data_snd_is_imm)
-					alu_b = {{20{1'b0}}, data_imm};
-				else
-					alu_b = rd_value_b;
-		endcase
+	core_control_mux mux
+	(
+		.*
+	);
 
+	always_comb
 		vector_offset = 3'b001; //TODO
-	end
 
 	always_ff @(posedge clk) begin
 		branch <= 0;
-- 
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