From ac0d6f4e068ff0ff08f05e04053ebd53ba20bcb8 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 8 Nov 2022 00:19:49 -0600 Subject: Refactor decode signals into unified insn_decode struct --- rtl/core/control/branch.sv | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) (limited to 'rtl/core/control/branch.sv') diff --git a/rtl/core/control/branch.sv b/rtl/core/control/branch.sv index 3f8160e..59a4f54 100644 --- a/rtl/core/control/branch.sv +++ b/rtl/core/control/branch.sv @@ -2,24 +2,23 @@ module core_control_branch ( - input logic clk, + input logic clk, - input datapath_decode dec, - input branch_decode dec_branch, + input insn_decode dec, - input ctrl_cycle next_cycle, - input logic issue, - input ptr next_pc_visible, + input ctrl_cycle next_cycle, + input logic issue, + input ptr next_pc_visible, - output logic branch, - output ptr branch_target + output logic branch, + output ptr branch_target ); always_ff @(posedge clk) begin branch <= 0; if(next_cycle == ISSUE && issue) begin - branch <= dec.branch; - branch_target <= next_pc_visible + dec_branch.offset; + branch <= dec.ctrl.branch; + branch_target <= next_pc_visible + dec.branch.offset; end end -- cgit v1.2.3