From 5d798386c3b1c1dc45a2fbc382c9367ccc27c524 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Wed, 9 Nov 2022 09:25:48 -0600
Subject: Implement reset

---
 rtl/core/control/branch.sv | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

(limited to 'rtl/core/control/branch.sv')

diff --git a/rtl/core/control/branch.sv b/rtl/core/control/branch.sv
index 59a4f54..96e6e65 100644
--- a/rtl/core/control/branch.sv
+++ b/rtl/core/control/branch.sv
@@ -3,6 +3,7 @@
 module core_control_branch
 (
 	input  logic       clk,
+	                   rst_n,
 
 	input  insn_decode dec,
 
@@ -14,17 +15,16 @@ module core_control_branch
 	output ptr         branch_target
 );
 
-	always_ff @(posedge clk) begin
-		branch <= 0;
-		if(next_cycle == ISSUE && issue) begin
-			branch <= dec.ctrl.branch;
-			branch_target <= next_pc_visible + dec.branch.offset;
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			branch <= 1;
+			branch_target <= {$bits(branch_target){1'b0}};
+		end else begin
+			branch <= 0;
+			if(next_cycle == ISSUE && issue) begin
+				branch <= dec.ctrl.branch;
+				branch_target <= next_pc_visible + dec.branch.offset;
+			end
 		end
-	end
-
-	initial begin
-		branch = 1;
-		branch_target = {$bits(branch_target){1'b0}};
-	end
 
 endmodule
-- 
cgit v1.2.3