From 29c6ca853ada52afbfcb2fd7d875572a56f16b4b Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Fri, 23 Sep 2022 23:40:40 -0600 Subject: Implement core stub It only has the fetch stage for now --- rtl/core/arm810.sv | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 rtl/core/arm810.sv (limited to 'rtl/core/arm810.sv') diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv new file mode 100644 index 0000000..cbb0244 --- /dev/null +++ b/rtl/core/arm810.sv @@ -0,0 +1,27 @@ +module arm810 +( + input logic clk, + + output logic[29:0] bus_addr, + output logic bus_start, + bus_write, + input logic bus_ready, + input logic[31:0] bus_data_rd, + output logic[31:0] bus_data_wr +); + + logic stall, prefetch_flush; + logic[31:0] insn; + logic[29:0] insn_pc; + + core_fetch #(.PREFETCH_ORDER(2)) fetch + ( + .flush(prefetch_flush), + .addr(bus_addr), + .fetched(bus_ready), + .fetch_data(bus_data_rd), + .fetch(bus_start), + .* + ); + +endmodule -- cgit v1.2.3