From b5f43ef8431532b1e0b498a88072fdfd2cf81ac9 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 25 Sep 2022 17:46:38 -0600 Subject: Implement ALU --- rtl/core/alu/and.sv | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 rtl/core/alu/and.sv (limited to 'rtl/core/alu/and.sv') diff --git a/rtl/core/alu/and.sv b/rtl/core/alu/and.sv new file mode 100644 index 0000000..d119f24 --- /dev/null +++ b/rtl/core/alu/and.sv @@ -0,0 +1,12 @@ +module core_alu_and +#(parameter W=16) +( + input logic[W - 1:0] a, + b, + + output logic[W - 1:0] q +); + + assign q = a & b; + +endmodule -- cgit v1.2.3