From 4448c8f77c87ad1ac34f42df2ef6ef91c36b54a6 Mon Sep 17 00:00:00 2001
From: JulianCamacho <jjulian.341@gmail.com>
Date: Wed, 4 Oct 2023 18:19:34 -0600
Subject: sram comment

---
 rtl/cache/sram.sv | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'rtl/cache')

diff --git a/rtl/cache/sram.sv b/rtl/cache/sram.sv
index 74f9e65..bd9140d 100644
--- a/rtl/cache/sram.sv
+++ b/rtl/cache/sram.sv
@@ -21,6 +21,8 @@ module cache_sram
 	// Existe un mito que habla de true dual-ports con byte-enables, dudo mucho que sea real:
 	// https://www.intel.com/content/www/us/en/docs/programmable/683082/21-3/ram-with-byte-enable-signals.html
 
+	// Define la cantidad de líneas de cache
+	// $bits(addr_index) = 9 --> 1 << 9 = 512
 	localparam DEPTH = 1 << $bits(addr_index);
 
 	line data_file[DEPTH] /*verilator public*/;
-- 
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