From 15230c6cd2190a1efd61c2758bf56de37f3fe8da Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 24 Sep 2023 20:58:04 -0600
Subject: rtl/cache: implement

---
 rtl/cache/defs.sv | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 64 insertions(+)
 create mode 100644 rtl/cache/defs.sv

(limited to 'rtl/cache/defs.sv')

diff --git a/rtl/cache/defs.sv b/rtl/cache/defs.sv
new file mode 100644
index 0000000..2566058
--- /dev/null
+++ b/rtl/cache/defs.sv
@@ -0,0 +1,64 @@
+`ifndef CACHE_DEFS_SV
+`define CACHE_DEFS_SV
+
+typedef logic[3:0]   word_be;
+typedef logic[15:0]  line_be;
+typedef logic[127:0] line;
+
+// Choca con typedef en core/uarch.sv
+`ifndef WORD_DEFINED
+typedef logic[31:0]  word;
+`define WORD_DEFINED
+`endif
+
+/* Tenemos 512MiB de SDRAM, el resto del espacio es I/O (uncached). Usamos
+* 512 líneas direct-mapped de 16 bytes cada una. El core solo realiza
+* operaciones alineadas. Por tanto, cada dirección de 32 bits consta de:
+ * - 2 bits que siempre son 0 (traducidos a byteenable por core)
+ * - 2 bits de offset (ya que para cache la unidad direccionable es la word)
+ * - 9 bits de index
+ * - 16 bits de tag
+ * - 3 bits que son == 0 si cached, != 0 si uncached
+ */
+typedef logic[1:0]  addr_mbz;
+typedef logic[1:0]  addr_offset;
+typedef logic[8:0]  addr_index;
+typedef logic[15:0] addr_tag;
+typedef logic[2:0]  addr_io_region;
+typedef logic[26:0] addr_cacheable;
+
+typedef enum logic[1:0]
+{
+	INVALID,
+	SHARED,
+	EXCLUSIVE,
+	MODIFIED
+} line_state;
+
+typedef struct packed
+{
+	logic[1:0] ttl;
+	logic      read,
+	           inval,
+	           reply;
+	addr_tag   tag;
+	addr_index index;
+	line       data;
+} ring_req;
+
+`define TTL_END 2'b00
+`define TTL_MAX 2'b11
+
+typedef struct packed
+{
+	logic      valid;
+	addr_tag   tag;
+	addr_index index;
+} token_lock;
+
+typedef struct packed
+{
+	token_lock e2, e1, e0;
+} ring_token;
+
+`endif
-- 
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