From d406720cecd7328f595255e65b6fd6b6814cefe4 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Thu, 5 Oct 2023 16:26:26 -0600 Subject: rtl/perf: implement performance unit --- rtl/cache/cache_control.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'rtl/cache/cache_control.sv') diff --git a/rtl/cache/cache_control.sv b/rtl/cache/cache_control.sv index b31b6a8..64b4ce1 100644 --- a/rtl/cache/cache_control.sv +++ b/rtl/cache/cache_control.sv @@ -80,7 +80,7 @@ module cache_control assign mem_end = (mem_read || mem_write) && !mem_waitrequest; assign mem_wait = (mem_read || mem_write) && mem_waitrequest; - assign mem_address = {3'b000, mem_tag, mem_index, 4'b0000}; + assign mem_address = {`IO_CACHED, mem_tag, mem_index, 4'b0000}; assign mem_read_end = mem_read && !mem_waitrequest; /* Desbloquear la línea hasta que la request del core termine garantiza -- cgit v1.2.3