From ed0bd705f94f6aea568ec8405534984a37770f21 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 25 Sep 2023 19:12:49 -0600
Subject: rtl/core, tb: replace bus_master with a new top-level module

---
 rtl/bus_master.sv | 73 -------------------------------------------------------
 1 file changed, 73 deletions(-)
 delete mode 100644 rtl/bus_master.sv

(limited to 'rtl/bus_master.sv')

diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
deleted file mode 100644
index 0c6af55..0000000
--- a/rtl/bus_master.sv
+++ /dev/null
@@ -1,73 +0,0 @@
-module bus_master
-(
-	input  logic       clk,
-	                   rst_n,
-
-	input  logic[29:0] addr,
-	input  logic       start,
-	                   write,
-	output logic       ready,
-	output logic[31:0] data_rd,
-	input  logic[31:0] data_wr,
-	input  logic[3:0]  data_be,
-	output logic       cpu_clk,
-	                   cpu_rst_n,
-	                   irq,
-
-	output logic[31:0] avl_address,
-	output logic       avl_read,
-	                   avl_write,
-	input  logic[31:0] avl_readdata,
-	output logic[31:0] avl_writedata,
-	input  logic       avl_waitrequest,
-	output logic[3:0]  avl_byteenable,
-	input  logic       avl_irq
-);
-
-	enum int unsigned
-	{
-		IDLE,
-		WAIT
-	} state;
-
-	assign irq = avl_irq;
-	assign cpu_clk = clk;
-	assign cpu_rst_n = rst_n;
-
-	assign data_rd = avl_readdata;
-
-	always_comb
-		unique case(state)
-			IDLE: ready = 0;
-			WAIT: ready = !avl_waitrequest;
-		endcase
-
-	always_ff @(posedge clk or negedge rst_n)
-		/* P. 16:
-		 * A host must make no assumption about the assertion state of
-		 * waitrequest when the host is idle: waitrequest may be high or
-		 * low, depending on system properties. When waitrequest is asserted,
-		 * host control signals to the agent must remain constant except for
-		 * beginbursttransfer.
-		 */
-		if(!rst_n) begin
-			state <= IDLE;
-			avl_read <= 0;
-			avl_write <= 0;
-			avl_address <= 0;
-			avl_writedata <= 0;
-			avl_byteenable <= 0;
-		end else if((state == IDLE || !avl_waitrequest) && start) begin
-			state <= WAIT;
-			avl_read <= ~write;
-			avl_write <= write;
-			avl_address <= {addr, 2'b00};
-			avl_writedata <= data_wr;
-			avl_byteenable <= write ? data_be : 4'b1111;
-		end else if(state == WAIT && !avl_waitrequest) begin
-			state <= IDLE;
-			avl_read <= 0;
-			avl_write <= 0;
-		end
-
-endmodule
-- 
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