From d9dfa098323bc9ffdc9e976bd4106efc75b2954a Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Tue, 15 Nov 2022 23:18:09 -0600
Subject: Implemente byte-enable signal in stores

---
 rtl/bus_master.sv | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

(limited to 'rtl/bus_master.sv')

diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
index 7775e42..0c6af55 100644
--- a/rtl/bus_master.sv
+++ b/rtl/bus_master.sv
@@ -9,6 +9,7 @@ module bus_master
 	output logic       ready,
 	output logic[31:0] data_rd,
 	input  logic[31:0] data_wr,
+	input  logic[3:0]  data_be,
 	output logic       cpu_clk,
 	                   cpu_rst_n,
 	                   irq,
@@ -34,7 +35,6 @@ module bus_master
 	assign cpu_rst_n = rst_n;
 
 	assign data_rd = avl_readdata;
-	assign avl_byteenable = 4'b1111; //TODO
 
 	always_comb
 		unique case(state)
@@ -56,12 +56,14 @@ module bus_master
 			avl_write <= 0;
 			avl_address <= 0;
 			avl_writedata <= 0;
+			avl_byteenable <= 0;
 		end else if((state == IDLE || !avl_waitrequest) && start) begin
 			state <= WAIT;
 			avl_read <= ~write;
 			avl_write <= write;
 			avl_address <= {addr, 2'b00};
 			avl_writedata <= data_wr;
+			avl_byteenable <= write ? data_be : 4'b1111;
 		end else if(state == WAIT && !avl_waitrequest) begin
 			state <= IDLE;
 			avl_read <= 0;
-- 
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