From d463acba5f9589085afb3dcc4058d82908ff90f2 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 13 Nov 2022 05:22:23 -0600
Subject: Convert core state machines to Quartus-inferring RTL

---
 rtl/bus_master.sv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'rtl/bus_master.sv')

diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
index c61a208..7775e42 100644
--- a/rtl/bus_master.sv
+++ b/rtl/bus_master.sv
@@ -23,7 +23,8 @@ module bus_master
 	input  logic       avl_irq
 );
 
-	enum {
+	enum int unsigned
+	{
 		IDLE,
 		WAIT
 	} state;
-- 
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