From acca3eb31a051f335c51306786bb972c21634998 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Thu, 10 Nov 2022 10:11:33 -0600 Subject: Fix reset glitches --- rtl/bus_master.sv | 2 ++ 1 file changed, 2 insertions(+) (limited to 'rtl/bus_master.sv') diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv index 0d1470d..0a2f2ea 100644 --- a/rtl/bus_master.sv +++ b/rtl/bus_master.sv @@ -51,6 +51,8 @@ module bus_master state <= IDLE; avl_read <= 0; avl_write <= 0; + avl_address <= 0; + avl_writedata <= 0; end else if((state == IDLE || !avl_waitrequest) && start) begin state <= WAIT; avl_read <= ~write; -- cgit v1.2.3