From abe3a7da04a3703bd504b5ed2e13ecc79dff4bd0 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Wed, 2 Nov 2022 23:48:21 -0600 Subject: Add bus master forward signals: irq, cpu_clk --- rtl/bus_master.sv | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'rtl/bus_master.sv') diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv index e4a76d2..560cb67 100644 --- a/rtl/bus_master.sv +++ b/rtl/bus_master.sv @@ -9,6 +9,8 @@ module bus_master output logic ready, output logic[31:0] data_rd, input logic[31:0] data_wr, + output logic cpu_clk, + irq, output logic[31:0] avl_address, output logic avl_read, @@ -16,7 +18,8 @@ module bus_master input logic[31:0] avl_readdata, output logic[31:0] avl_writedata, input logic avl_waitrequest, - output logic[3:0] avl_byteenable + output logic[3:0] avl_byteenable, + input logic avl_irq ); enum { @@ -24,6 +27,9 @@ module bus_master WAIT } state; + assign irq = avl_irq; + assign cpu_clk = clk; + assign data_rd = avl_readdata; assign avl_byteenable = 4'b1111; //TODO -- cgit v1.2.3