From 9a1dd87d89d3cb57fe0d811e462b9348234eae79 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 12 Nov 2022 21:25:37 -0600 Subject: Route cpu_rst_n signal through bus master --- rtl/bus_master.sv | 2 ++ 1 file changed, 2 insertions(+) (limited to 'rtl/bus_master.sv') diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv index 0a2f2ea..c61a208 100644 --- a/rtl/bus_master.sv +++ b/rtl/bus_master.sv @@ -10,6 +10,7 @@ module bus_master output logic[31:0] data_rd, input logic[31:0] data_wr, output logic cpu_clk, + cpu_rst_n, irq, output logic[31:0] avl_address, @@ -29,6 +30,7 @@ module bus_master assign irq = avl_irq; assign cpu_clk = clk; + assign cpu_rst_n = rst_n; assign data_rd = avl_readdata; assign avl_byteenable = 4'b1111; //TODO -- cgit v1.2.3