From b0cb20496d88cd017c4c51243d16ac3b060cc1d6 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sat, 17 Sep 2022 22:10:39 -0600 Subject: Update project structure to match Verilator Makefile --- rtl/bus/master.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'rtl/bus') diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv index 63ea2be..5d8c3a8 100644 --- a/rtl/bus/master.sv +++ b/rtl/bus/master.sv @@ -49,10 +49,10 @@ module bus_master endcase initial begin - ready <= 0; - avl_read <= 0; - avl_write <= 0; - state <= REQUEST; + ready = 0; + avl_read = 0; + avl_write = 0; + state = REQUEST; end endmodule -- cgit v1.2.3