From b762fc978a49910986e00e6c08e0afbe1e612858 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 18 Sep 2022 19:07:24 -0600
Subject: Rename data_rw to data_wr in bus master

---
 rtl/bus/master.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'rtl/bus/master.sv')

diff --git a/rtl/bus/master.sv b/rtl/bus/master.sv
index d350d80..6e29ac2 100644
--- a/rtl/bus/master.sv
+++ b/rtl/bus/master.sv
@@ -8,7 +8,7 @@ module bus_master
 	                   write,
 	output logic       ready,
 	output logic[31:0] data_rd,
-	input  logic[31:0] data_rw,
+	input  logic[31:0] data_wr,
 
 	output logic[31:0] avl_address,
 	output logic       avl_read,
@@ -33,7 +33,7 @@ module bus_master
 			avl_address <= {addr, 2'b00};
 			avl_read <= ~write;
 			avl_write <= write;
-			avl_writedata <= data_rw;
+			avl_writedata <= data_wr;
 			state <= WAIT;
 		end
 
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