From 50b71c7f0ea2574eb4802e1a12fe8b0920a4ca7f Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sat, 27 Apr 2024 12:14:41 -0600
Subject: rtl/axi_timer: initial commit

This a buggy timer, imported from https://github.com/astrakhov-design/axi_timer.
It will be used for a testbench hello world case
---
 rtl/axi_timer/axi_timer_top.sv | 45 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)
 create mode 100644 rtl/axi_timer/axi_timer_top.sv

(limited to 'rtl/axi_timer/axi_timer_top.sv')

diff --git a/rtl/axi_timer/axi_timer_top.sv b/rtl/axi_timer/axi_timer_top.sv
new file mode 100644
index 0000000..6bd0e2a
--- /dev/null
+++ b/rtl/axi_timer/axi_timer_top.sv
@@ -0,0 +1,45 @@
+module axi_timer_top
+(
+	input  logic       clk,
+	                   rst_n,
+
+	input  logic[31:0] addr,
+	input  logic       avalid,
+	input  logic       awrite,
+	output logic       aready,
+
+	input  logic       wvalid,
+	input  logic[31:0] wdata,
+	output logic       wready,
+
+	input  logic       rready,
+	output logic[31:0] rdata,
+	output logic       rvalid,
+
+	output logic       irq
+);
+
+	axi_bus axi();
+
+	assign axi.Master.ADDR = addr;
+	assign axi.Master.AVALID = avalid;
+	assign axi.Master.AWRITE = awrite;
+	assign aready = axi.Master.AREADY;
+
+	assign axi.Master.WVALID = wvalid;
+	assign axi.Master.WDATA = wdata;
+	assign wready = axi.Master.WREADY;
+
+	assign axi.Master.RREADY = rready;
+	assign rdata = axi.Master.RDATA;
+	assign rvalid = axi.Master.RVALID;
+
+	axi_timer timer
+	(
+		.i_clk(clk),
+		.i_rst_n(rst_n),
+		.o_IRQ(irq),
+		.axi_slave(axi.Slave)
+	);
+
+endmodule
-- 
cgit v1.2.3