From 4fdcb079663eccc71ed2c120f8279d6c364de9fd Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sat, 4 May 2024 23:58:08 -0600
Subject: platform/wavelet3d: implement shader writeback

---
 platform/wavelet3d/gfx_shader_schedif.rdl | 27 ++++++++++++++++++++++-----
 1 file changed, 22 insertions(+), 5 deletions(-)

(limited to 'platform/wavelet3d/gfx_shader_schedif.rdl')

diff --git a/platform/wavelet3d/gfx_shader_schedif.rdl b/platform/wavelet3d/gfx_shader_schedif.rdl
index 2ab31ac..c846da9 100644
--- a/platform/wavelet3d/gfx_shader_schedif.rdl
+++ b/platform/wavelet3d/gfx_shader_schedif.rdl
@@ -13,12 +13,12 @@ addrmap gfx_shader_schedif {
 
             singlepulse;
         } IFLUSH[0:0] = 0;
-    } CORE @ 0x0;
+    } CORE @ 0x00;
 
     reg {
         name = "Wavefront setup control register";
 
-        default hw = w;
+        default hw = na;
         default sw = r;
         default precedence = hw;
 
@@ -49,7 +49,14 @@ addrmap gfx_shader_schedif {
             rclr;
             hwset;
         } GPR_DONE[17:17] = 0;
-    } SETUP_CTRL @ 0x4;
+
+        field {
+            desc = "Lane mask update done";
+
+            rclr;
+            hwset;
+        } MASK_DONE[18:18] = 0;
+    } SETUP_CTRL @ 0x04;
 
     reg {
         name = "SGPR/VGPR write register";
@@ -59,7 +66,17 @@ addrmap gfx_shader_schedif {
 
             swmod;
         } VALUE[31:0];
-    } SETUP_GPR @ 0x8;
+    } SETUP_GPR @ 0x08;
+
+    reg {
+        name = "Lane mask write register";
+
+        field {
+            desc = "Mask value to write";
+
+            swmod;
+        } MASK[15:0];
+    } SETUP_MASK @ 0x0c;
 
     reg {
         name = "Group submit register";
@@ -69,6 +86,6 @@ addrmap gfx_shader_schedif {
 
             swmod;
         } PC[31:2];
-    } SETUP_SUBMIT @ 0xc;
+    } SETUP_SUBMIT @ 0x10;
 };
 
-- 
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