From 986863efed48dfba23907400beb7e5f025b75b50 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 26 Oct 2023 01:33:00 -0600
Subject: rtl/gfx: synchronize clock with SDRAM

---
 platform.qsys | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)

(limited to 'platform.qsys')

diff --git a/platform.qsys b/platform.qsys
index f0724b0..21cc3e9 100644
--- a/platform.qsys
+++ b/platform.qsys
@@ -1491,11 +1491,6 @@
   <parameter name="baseAddress" value="0x30020000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection kind="avalon" version="20.1" start="mm_bridge.m0" end="vram.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x38000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="avalon"
    version="20.1"
@@ -1692,7 +1687,6 @@
    end="hps_0.f2h_sdram0_clock" />
  <connection kind="clock" version="20.1" start="pll_0.outclk1" end="mm_bridge.clk" />
  <connection kind="clock" version="20.1" start="pll_0.outclk1" end="smp_0.clock" />
- <connection kind="clock" version="20.1" start="pll_0.outclk1" end="gfx_0.clock" />
  <connection
    kind="clock"
    version="20.1"
@@ -1753,6 +1747,11 @@
    version="20.1"
    start="sys_sdram_pll_0.sys_clk"
    end="pixfmt.clk" />
+ <connection
+   kind="clock"
+   version="20.1"
+   start="sys_sdram_pll_0.sys_clk"
+   end="gfx_0.clock" />
  <connection
    kind="clock"
    version="20.1"
-- 
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