From c2ddefda2ed6badddac5c229f59fcb25860759a4 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 20 Nov 2023 18:47:55 -0600
Subject: rtl/gfx: remove gfx_{perspective{,_flow}, fp_inv}

---
 ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl        | 278 -------
 ip/ip_fp_inv_sim/cadence/cds.lib                   |  19 -
 ip/ip_fp_inv_sim/cadence/hdl.var                   |   2 -
 ip/ip_fp_inv_sim/cadence/ncsim_setup.sh            | 195 -----
 ip/ip_fp_inv_sim/ip_fp_inv.vo                      | 862 ---------------------
 ip/ip_fp_inv_sim/mentor/msim_setup.tcl             | 272 -------
 ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh         | 152 ----
 ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup |  13 -
 ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh     | 195 -----
 9 files changed, 1988 deletions(-)
 delete mode 100644 ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl
 delete mode 100644 ip/ip_fp_inv_sim/cadence/cds.lib
 delete mode 100644 ip/ip_fp_inv_sim/cadence/hdl.var
 delete mode 100755 ip/ip_fp_inv_sim/cadence/ncsim_setup.sh
 delete mode 100644 ip/ip_fp_inv_sim/ip_fp_inv.vo
 delete mode 100644 ip/ip_fp_inv_sim/mentor/msim_setup.tcl
 delete mode 100755 ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh
 delete mode 100644 ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup
 delete mode 100755 ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh

(limited to 'ip/ip_fp_inv_sim')

diff --git a/ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl b/ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl
deleted file mode 100644
index 58382a2..0000000
--- a/ip/ip_fp_inv_sim/aldec/rivierapro_setup.tcl
+++ /dev/null
@@ -1,278 +0,0 @@
-
-# (C) 2001-2023 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-# ----------------------------------------
-# Auto-generated simulation script rivierapro_setup.tcl
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     ip_fp_inv
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level script that compiles Altera simulation libraries and
-# the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "aldec.do", and modify the text as directed.
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator.
-# #
-# set QSYS_SIMDIR <script generation output directory>
-# #
-# # Source the generated IP simulation script.
-# source $QSYS_SIMDIR/aldec/rivierapro_setup.tcl
-# #
-# # Set any compilation options you require (this is unusual).
-# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
-# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
-# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
-# #
-# # Call command to compile the Quartus EDA simulation library.
-# dev_com
-# #
-# # Call command to compile the Quartus-generated IP simulation files.
-# com
-# #
-# # Add commands to compile all design files and testbench files, including
-# # the top level. (These are all the files required for simulation other
-# # than the files compiled by the Quartus-generated IP simulation script)
-# #
-# vlog -sv2k5 <your compilation options> <design and testbench files>
-# #
-# # Set the top-level simulation or testbench module/entity name, which is
-# # used by the elab command to elaborate the top level.
-# #
-# set TOP_LEVEL_NAME <simulation top>
-# #
-# # Set any elaboration options you require.
-# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
-# #
-# # Call command to elaborate your design and testbench.
-# elab
-# #
-# # Run the simulation.
-# run
-# #
-# # Report success to the shell.
-# exit -code 0
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If ip_fp_inv is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-
-# ----------------------------------------
-# Initialize variables
-if ![info exists SYSTEM_INSTANCE_NAME] { 
-  set SYSTEM_INSTANCE_NAME ""
-} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
-  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
-}
-
-if ![info exists TOP_LEVEL_NAME] { 
-  set TOP_LEVEL_NAME "ip_fp_inv"
-}
-
-if ![info exists QSYS_SIMDIR] { 
-  set QSYS_SIMDIR "./../"
-}
-
-if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
-}
-
-if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
-  set USER_DEFINED_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
-  set USER_DEFINED_ELAB_OPTIONS ""
-}
-
-# ----------------------------------------
-# Initialize simulation properties - DO NOT MODIFY!
-set ELAB_OPTIONS ""
-set SIM_OPTIONS ""
-if ![ string match "*-64 vsim*" [ vsim -version ] ] {
-} else {
-}
-
-set Aldec "Riviera"
-if { [ string match "*Active-HDL*" [ vsim -version ] ] } {
-  set Aldec "Active"
-}
-
-if { [ string match "Active" $Aldec ] } {
-  scripterconf -tcl
-  createdesign "$TOP_LEVEL_NAME"  "."
-  opendesign "$TOP_LEVEL_NAME"
-}
-
-# ----------------------------------------
-# Copy ROM/RAM files to simulation directory
-alias file_copy {
-  echo "\[exec\] file_copy"
-}
-
-# ----------------------------------------
-# Create compilation libraries
-proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
-ensure_lib      ./libraries     
-ensure_lib      ./libraries/work
-vmap       work ./libraries/work
-ensure_lib                       ./libraries/altera_ver           
-vmap       altera_ver            ./libraries/altera_ver           
-ensure_lib                       ./libraries/lpm_ver              
-vmap       lpm_ver               ./libraries/lpm_ver              
-ensure_lib                       ./libraries/sgate_ver            
-vmap       sgate_ver             ./libraries/sgate_ver            
-ensure_lib                       ./libraries/altera_mf_ver        
-vmap       altera_mf_ver         ./libraries/altera_mf_ver        
-ensure_lib                       ./libraries/altera_lnsim_ver     
-vmap       altera_lnsim_ver      ./libraries/altera_lnsim_ver     
-ensure_lib                       ./libraries/cyclonev_ver         
-vmap       cyclonev_ver          ./libraries/cyclonev_ver         
-ensure_lib                       ./libraries/cyclonev_hssi_ver    
-vmap       cyclonev_hssi_ver     ./libraries/cyclonev_hssi_ver    
-ensure_lib                       ./libraries/cyclonev_pcie_hip_ver
-vmap       cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver
-
-
-# ----------------------------------------
-# Compile device library files
-alias dev_com {
-  echo "\[exec\] dev_com"
-  eval vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                    -work altera_ver           
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                             -work lpm_ver              
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                -work sgate_ver            
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                            -work altera_mf_ver        
-  vlog  $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS      "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                        -work altera_lnsim_ver     
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                       -work cyclonev_ver         
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                  -work cyclonev_hssi_ver    
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/aldec/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
-  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"              -work cyclonev_pcie_hip_ver
-}
-
-# ----------------------------------------
-# Compile the design files in correct order
-alias com {
-  echo "\[exec\] com"
-  eval  vlog -v2k5 $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
-}
-
-# ----------------------------------------
-# Elaborate top level design
-alias elab {
-  echo "\[exec\] elab"
-  eval vsim +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Elaborate the top level design with -dbg -O2 option
-alias elab_debug {
-  echo "\[exec\] elab_debug"
-  eval vsim -dbg -O2 +access +r -t ps $ELAB_OPTIONS -L work -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design
-alias ld "
-  dev_com
-  com
-  elab
-"
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design with -dbg -O2
-alias ld_debug "
-  dev_com
-  com
-  elab_debug
-"
-
-# ----------------------------------------
-# Print out user commmand line aliases
-alias h {
-  echo "List Of Command Line Aliases"
-  echo
-  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
-  echo
-  echo "dev_com                                           -- Compile device library files"
-  echo
-  echo "com                                               -- Compile the design files in correct order"
-  echo
-  echo "elab                                              -- Elaborate top level design"
-  echo
-  echo "elab_debug                                        -- Elaborate the top level design with -dbg -O2 option"
-  echo
-  echo "ld                                                -- Compile all the design files and elaborate the top level design"
-  echo
-  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -dbg -O2"
-  echo
-  echo 
-  echo
-  echo "List Of Variables"
-  echo
-  echo "TOP_LEVEL_NAME                                    -- Top level module name."
-  echo "                                                     For most designs, this should be overridden"
-  echo "                                                     to enable the elab/elab_debug aliases."
-  echo
-  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
-  echo
-  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
-  echo
-  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
-  echo
-  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
-  echo
-  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
-}
-file_copy
-h
diff --git a/ip/ip_fp_inv_sim/cadence/cds.lib b/ip/ip_fp_inv_sim/cadence/cds.lib
deleted file mode 100644
index b2eae0a..0000000
--- a/ip/ip_fp_inv_sim/cadence/cds.lib
+++ /dev/null
@@ -1,19 +0,0 @@
-
-DEFINE std                   $CDS_ROOT/tools/inca/files/STD/           
-DEFINE synopsys              $CDS_ROOT/tools/inca/files/SYNOPSYS/      
-DEFINE ieee                  $CDS_ROOT/tools/inca/files/IEEE/          
-DEFINE ambit                 $CDS_ROOT/tools/inca/files/AMBIT/         
-DEFINE vital_memory          $CDS_ROOT/tools/inca/files/VITAL_MEMORY/  
-DEFINE ncutils               $CDS_ROOT/tools/inca/files/NCUTILS/       
-DEFINE ncinternal            $CDS_ROOT/tools/inca/files/NCINTERNAL/    
-DEFINE ncmodels              $CDS_ROOT/tools/inca/files/NCMODELS/      
-DEFINE cds_assertions        $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
-DEFINE work                  ./libraries/work/                         
-DEFINE altera_ver            ./libraries/altera_ver/                   
-DEFINE lpm_ver               ./libraries/lpm_ver/                      
-DEFINE sgate_ver             ./libraries/sgate_ver/                    
-DEFINE altera_mf_ver         ./libraries/altera_mf_ver/                
-DEFINE altera_lnsim_ver      ./libraries/altera_lnsim_ver/             
-DEFINE cyclonev_ver          ./libraries/cyclonev_ver/                 
-DEFINE cyclonev_hssi_ver     ./libraries/cyclonev_hssi_ver/            
-DEFINE cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/        
diff --git a/ip/ip_fp_inv_sim/cadence/hdl.var b/ip/ip_fp_inv_sim/cadence/hdl.var
deleted file mode 100644
index c1b7814..0000000
--- a/ip/ip_fp_inv_sim/cadence/hdl.var
+++ /dev/null
@@ -1,2 +0,0 @@
-
-DEFINE WORK work
diff --git a/ip/ip_fp_inv_sim/cadence/ncsim_setup.sh b/ip/ip_fp_inv_sim/cadence/ncsim_setup.sh
deleted file mode 100755
index ccdef9e..0000000
--- a/ip/ip_fp_inv_sim/cadence/ncsim_setup.sh
+++ /dev/null
@@ -1,195 +0,0 @@
-
-# (C) 2001-2023 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-
-# ----------------------------------------
-# ncsim - auto-generated simulation script
-
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     ip_fp_inv
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level shell script that compiles Altera simulation libraries
-# and the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "ncsim.sh", and modify text as directed.
-# 
-# You can also modify the simulation flow to suit your needs. Set the
-# following variables to 1 to disable their corresponding processes:
-# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
-# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
-# - SKIP_COM: skip compiling Quartus-generated IP simulation files
-# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator. In this case, you must also copy the generated files
-# # "cds.lib" and "hdl.var" - plus the directory "cds_libs" if generated - 
-# # into the location from which you launch the simulator, or incorporate
-# # into any existing library setup.
-# #
-# # Run Quartus-generated IP simulation script once to compile Quartus EDA
-# # simulation libraries and Quartus-generated IP simulation files, and copy
-# # any ROM/RAM initialization files to the simulation directory.
-# # - If necessary, specify any compilation options:
-# #   USER_DEFINED_COMPILE_OPTIONS
-# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
-# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
-# #
-# source <script generation output directory>/cadence/ncsim_setup.sh \
-# SKIP_ELAB=1 \
-# SKIP_SIM=1 \
-# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
-# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
-# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
-# QSYS_SIMDIR=<script generation output directory>
-# #
-# # Compile all design files and testbench files, including the top level.
-# # (These are all the files required for simulation other than the files
-# # compiled by the IP script)
-# #
-# ncvlog <compilation options> <design and testbench files>
-# #
-# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
-# # testbench module/entity name.
-# #
-# # Run the IP script again to elaborate and simulate the top level:
-# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
-# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
-# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
-# #
-# source <script generation output directory>/cadence/ncsim_setup.sh \
-# SKIP_FILE_COPY=1 \
-# SKIP_DEV_COM=1 \
-# SKIP_COM=1 \
-# TOP_LEVEL_NAME=<simulation top> \
-# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
-# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If ip_fp_inv is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-# ----------------------------------------
-# initialize variables
-TOP_LEVEL_NAME="ip_fp_inv"
-QSYS_SIMDIR="./../"
-QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
-SKIP_FILE_COPY=0
-SKIP_DEV_COM=0
-SKIP_COM=0
-SKIP_ELAB=0
-SKIP_SIM=0
-USER_DEFINED_ELAB_OPTIONS=""
-USER_DEFINED_SIM_OPTIONS="-input \"@run 100; exit\""
-
-# ----------------------------------------
-# overwrite variables - DO NOT MODIFY!
-# This block evaluates each command line argument, typically used for 
-# overwriting variables. An example usage:
-#   sh <simulator>_setup.sh SKIP_SIM=1
-for expression in "$@"; do
-  eval $expression
-  if [ $? -ne 0 ]; then
-    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
-    exit $?
-  fi
-done
-
-# ----------------------------------------
-# initialize simulation properties - DO NOT MODIFY!
-ELAB_OPTIONS=""
-SIM_OPTIONS=""
-if [[ `ncsim -version` != *"ncsim(64)"* ]]; then
-  :
-else
-  :
-fi
-
-# ----------------------------------------
-# create compilation libraries
-mkdir -p ./libraries/work/
-mkdir -p ./libraries/altera_ver/
-mkdir -p ./libraries/lpm_ver/
-mkdir -p ./libraries/sgate_ver/
-mkdir -p ./libraries/altera_mf_ver/
-mkdir -p ./libraries/altera_lnsim_ver/
-mkdir -p ./libraries/cyclonev_ver/
-mkdir -p ./libraries/cyclonev_hssi_ver/
-mkdir -p ./libraries/cyclonev_pcie_hip_ver/
-
-# ----------------------------------------
-# copy RAM/ROM files to simulation directory
-
-# ----------------------------------------
-# compile device library files
-if [ $SKIP_DEV_COM -eq 0 ]; then
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                      -work altera_ver           
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                               -work lpm_ver              
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                  -work sgate_ver            
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                              -work altera_mf_ver        
-  ncvlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                          -work altera_lnsim_ver     
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                         -work cyclonev_ver         
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                    -work cyclonev_hssi_ver    
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cadence/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"                -work cyclonev_pcie_hip_ver
-fi
-
-# ----------------------------------------
-# compile design files in correct order
-if [ $SKIP_COM -eq 0 ]; then
-  ncvlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
-fi
-
-# ----------------------------------------
-# elaborate top level design
-if [ $SKIP_ELAB -eq 0 ]; then
-  export GENERIC_PARAM_COMPAT_CHECK=1
-  ncelab -access +w+r+c -namemap_mixgen -relax $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
-fi
-
-# ----------------------------------------
-# simulate
-if [ $SKIP_SIM -eq 0 ]; then
-  eval ncsim -licqueue $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS $TOP_LEVEL_NAME
-fi
diff --git a/ip/ip_fp_inv_sim/ip_fp_inv.vo b/ip/ip_fp_inv_sim/ip_fp_inv.vo
deleted file mode 100644
index 212c7fa..0000000
--- a/ip/ip_fp_inv_sim/ip_fp_inv.vo
+++ /dev/null
@@ -1,862 +0,0 @@
-//IP Functional Simulation Model
-//VERSION_BEGIN 20.1 cbx_mgl 2020:11:11:17:50:46:SJ cbx_simgen 2020:11:11:17:03:37:SJ  VERSION_END
-// synthesis VERILOG_INPUT_VERSION VERILOG_2001
-// altera message_off 10463
-
-
-
-// Copyright (C) 2020  Intel Corporation. All rights reserved.
-// Your use of Intel Corporation's design tools, logic functions 
-// and other software and tools, and any partner logic 
-// functions, and any output files from any of the foregoing 
-// (including device programming or simulation files), and any 
-// associated documentation or information are expressly subject 
-// to the terms and conditions of the Intel Program License 
-// Subscription Agreement, the Intel Quartus Prime License Agreement,
-// the Intel FPGA IP License Agreement, or other applicable license
-// agreement, including, without limitation, that your use is for
-// the sole purpose of programming logic devices manufactured by
-// Intel and sold by Intel or its authorized distributors.  Please
-// refer to the applicable agreement for further details, at
-// https://fpgasoftware.intel.com/eula.
-
-// You may only use these simulation model output files for simulation
-// purposes and expressly not for synthesis or any other purposes (in which
-// event Intel disclaims all warranties of any kind).
-
-
-//synopsys translate_off
-
-//synthesis_resources = lut 80 mux21 15 oper_add 3 oper_mult 1 oper_mux 40 
-`timescale 1 ps / 1 ps
-module  ip_fp_inv
-	( 
-	a,
-	areset,
-	clk,
-	en,
-	q) /* synthesis synthesis_clearbox=1 */;
-	input   [15:0]  a;
-	input   areset;
-	input   clk;
-	input   [0:0]  en;
-	output   [15:0]  q;
-
-	reg	n00l;
-	reg	n00O;
-	reg	n0i;
-	reg	n0ii;
-	reg	n0il;
-	reg	n0iO;
-	reg	n0li;
-	reg	n0ll;
-	reg	n0lO;
-	reg	n0O;
-	reg	n0Oi;
-	reg	n0Ol;
-	reg	n0OO;
-	reg	n1iO;
-	reg	n1l;
-	reg	n1li;
-	reg	n1ll;
-	reg	n1O;
-	reg	n1Ol;
-	reg	ni0i;
-	reg	ni0l;
-	reg	ni0O;
-	reg	ni1i;
-	reg	ni1l;
-	reg	ni1O;
-	reg	niii;
-	reg	niil;
-	reg	niili;
-	reg	niill;
-	reg	niilO;
-	reg	niiO;
-	reg	niiOi;
-	reg	niiOl;
-	reg	niiOO;
-	reg	nil0i;
-	reg	nil0l;
-	reg	nil0O;
-	reg	nil1i;
-	reg	nil1l;
-	reg	nil1O;
-	reg	nili;
-	reg	nilii;
-	reg	nilil;
-	reg	niliO;
-	reg	nill;
-	reg	nilli;
-	reg	nilll;
-	reg	nillO;
-	reg	nilOi;
-	reg	nilOl;
-	reg	nilOO;
-	reg	niO0i;
-	reg	niO0l;
-	reg	niO0O;
-	reg	niO1i;
-	reg	niO1l;
-	reg	niO1O;
-	reg	niOii;
-	reg	niOil;
-	reg	niOiO;
-	reg	niOli;
-	reg	niOll;
-	reg	niOlO;
-	reg	niOOi;
-	reg	niOOl;
-	reg	niOOO;
-	reg	nl11i;
-	reg	nl11l;
-	reg	nlO0i;
-	reg	nlO0O;
-	reg	nlO1l;
-	reg	nlOii;
-	reg	nlOil;
-	reg	nlOiO;
-	reg	nlOli;
-	reg	nlOll;
-	reg	nlOlO;
-	reg	nlOOi;
-	wire	wire_n0l_ENA;
-	reg	n1Oi;
-	reg	nlO0l;
-	wire	wire_n1lO_ENA;
-	wire	wire_nii_dataout;
-	wire	wire_nil_dataout;
-	wire	wire_niO_dataout;
-	wire	wire_nli_dataout;
-	wire	wire_nll_dataout;
-	wire	wire_nllii_dataout;
-	wire	wire_nllil_dataout;
-	wire	wire_nlliO_dataout;
-	wire	wire_nllli_dataout;
-	wire	wire_nllll_dataout;
-	wire	wire_nlllO_dataout;
-	wire	wire_nllOi_dataout;
-	wire	wire_nllOl_dataout;
-	wire	wire_nllOO_dataout;
-	wire	wire_nlO1i_dataout;
-	wire  [6:0]   wire_ni_o;
-	wire  [6:0]   wire_nlO_o;
-	wire  [16:0]   wire_nlO1O_o;
-	wire  [13:0]   wire_nilO_o;
-	wire  wire_n00i_o;
-	wire  wire_n01i_o;
-	wire  wire_n01l_o;
-	wire  wire_n01O_o;
-	wire  wire_n10i_o;
-	wire  wire_n10l_o;
-	wire  wire_n10O_o;
-	wire  wire_n11i_o;
-	wire  wire_n11l_o;
-	wire  wire_n11O_o;
-	wire  wire_n1ii_o;
-	wire  wire_n1il_o;
-	wire  wire_n1OO_o;
-	wire  wire_niOi_o;
-	wire  wire_niOl_o;
-	wire  wire_niOO_o;
-	wire  wire_nl0i_o;
-	wire  wire_nl0l_o;
-	wire  wire_nl0O_o;
-	wire  wire_nl1i_o;
-	wire  wire_nl1l_o;
-	wire  wire_nl1O_o;
-	wire  wire_nlii_o;
-	wire  wire_nlil_o;
-	wire  wire_nlilO_o;
-	wire  wire_nliO_o;
-	wire  wire_nliOi_o;
-	wire  wire_nliOl_o;
-	wire  wire_nliOO_o;
-	wire  wire_nll0i_o;
-	wire  wire_nll0l_o;
-	wire  wire_nll0O_o;
-	wire  wire_nll1i_o;
-	wire  wire_nll1l_o;
-	wire  wire_nll1O_o;
-	wire  wire_nlli_o;
-	wire  wire_nlll_o;
-	wire  wire_nllO_o;
-	wire  wire_nlOOl_o;
-	wire  wire_nlOOO_o;
-	wire  nii0i;
-	wire  nii0l;
-	wire  nii0O;
-	wire  nii1l;
-	wire  nii1O;
-	wire  niiii;
-
-	initial
-	begin
-		n00l = 0;
-		n00O = 0;
-		n0i = 0;
-		n0ii = 0;
-		n0il = 0;
-		n0iO = 0;
-		n0li = 0;
-		n0ll = 0;
-		n0lO = 0;
-		n0O = 0;
-		n0Oi = 0;
-		n0Ol = 0;
-		n0OO = 0;
-		n1iO = 0;
-		n1l = 0;
-		n1li = 0;
-		n1ll = 0;
-		n1O = 0;
-		n1Ol = 0;
-		ni0i = 0;
-		ni0l = 0;
-		ni0O = 0;
-		ni1i = 0;
-		ni1l = 0;
-		ni1O = 0;
-		niii = 0;
-		niil = 0;
-		niili = 0;
-		niill = 0;
-		niilO = 0;
-		niiO = 0;
-		niiOi = 0;
-		niiOl = 0;
-		niiOO = 0;
-		nil0i = 0;
-		nil0l = 0;
-		nil0O = 0;
-		nil1i = 0;
-		nil1l = 0;
-		nil1O = 0;
-		nili = 0;
-		nilii = 0;
-		nilil = 0;
-		niliO = 0;
-		nill = 0;
-		nilli = 0;
-		nilll = 0;
-		nillO = 0;
-		nilOi = 0;
-		nilOl = 0;
-		nilOO = 0;
-		niO0i = 0;
-		niO0l = 0;
-		niO0O = 0;
-		niO1i = 0;
-		niO1l = 0;
-		niO1O = 0;
-		niOii = 0;
-		niOil = 0;
-		niOiO = 0;
-		niOli = 0;
-		niOll = 0;
-		niOlO = 0;
-		niOOi = 0;
-		niOOl = 0;
-		niOOO = 0;
-		nl11i = 0;
-		nl11l = 0;
-		nlO0i = 0;
-		nlO0O = 0;
-		nlO1l = 0;
-		nlOii = 0;
-		nlOil = 0;
-		nlOiO = 0;
-		nlOli = 0;
-		nlOll = 0;
-		nlOlO = 0;
-		nlOOi = 0;
-	end
-	always @ ( posedge clk or  posedge areset)
-	begin
-		if (areset == 1'b1) 
-		begin
-			n00l <= 0;
-			n00O <= 0;
-			n0i <= 0;
-			n0ii <= 0;
-			n0il <= 0;
-			n0iO <= 0;
-			n0li <= 0;
-			n0ll <= 0;
-			n0lO <= 0;
-			n0O <= 0;
-			n0Oi <= 0;
-			n0Ol <= 0;
-			n0OO <= 0;
-			n1iO <= 0;
-			n1l <= 0;
-			n1li <= 0;
-			n1ll <= 0;
-			n1O <= 0;
-			n1Ol <= 0;
-			ni0i <= 0;
-			ni0l <= 0;
-			ni0O <= 0;
-			ni1i <= 0;
-			ni1l <= 0;
-			ni1O <= 0;
-			niii <= 0;
-			niil <= 0;
-			niili <= 0;
-			niill <= 0;
-			niilO <= 0;
-			niiO <= 0;
-			niiOi <= 0;
-			niiOl <= 0;
-			niiOO <= 0;
-			nil0i <= 0;
-			nil0l <= 0;
-			nil0O <= 0;
-			nil1i <= 0;
-			nil1l <= 0;
-			nil1O <= 0;
-			nili <= 0;
-			nilii <= 0;
-			nilil <= 0;
-			niliO <= 0;
-			nill <= 0;
-			nilli <= 0;
-			nilll <= 0;
-			nillO <= 0;
-			nilOi <= 0;
-			nilOl <= 0;
-			nilOO <= 0;
-			niO0i <= 0;
-			niO0l <= 0;
-			niO0O <= 0;
-			niO1i <= 0;
-			niO1l <= 0;
-			niO1O <= 0;
-			niOii <= 0;
-			niOil <= 0;
-			niOiO <= 0;
-			niOli <= 0;
-			niOll <= 0;
-			niOlO <= 0;
-			niOOi <= 0;
-			niOOl <= 0;
-			niOOO <= 0;
-			nl11i <= 0;
-			nl11l <= 0;
-			nlO0i <= 0;
-			nlO0O <= 0;
-			nlO1l <= 0;
-			nlOii <= 0;
-			nlOil <= 0;
-			nlOiO <= 0;
-			nlOli <= 0;
-			nlOll <= 0;
-			nlOlO <= 0;
-			nlOOi <= 0;
-		end
-		else if  (wire_n0l_ENA == 1'b1) 
-		begin
-			n00l <= wire_nilO_o[5];
-			n00O <= wire_nilO_o[6];
-			n0i <= wire_nli_dataout;
-			n0ii <= wire_nilO_o[7];
-			n0il <= wire_nilO_o[8];
-			n0iO <= wire_nilO_o[9];
-			n0li <= wire_nilO_o[10];
-			n0ll <= wire_nilO_o[11];
-			n0lO <= wire_nilO_o[13];
-			n0O <= wire_nll_dataout;
-			n0Oi <= wire_niOi_o;
-			n0Ol <= wire_niOl_o;
-			n0OO <= wire_niOO_o;
-			n1iO <= wire_n01i_o;
-			n1l <= wire_nil_dataout;
-			n1li <= wire_n01l_o;
-			n1ll <= wire_n01O_o;
-			n1O <= wire_niO_dataout;
-			n1Ol <= wire_nilO_o[4];
-			ni0i <= wire_nl0i_o;
-			ni0l <= wire_nl0l_o;
-			ni0O <= niiii;
-			ni1i <= wire_nl1i_o;
-			ni1l <= wire_nl1l_o;
-			ni1O <= wire_nl1O_o;
-			niii <= a[0];
-			niil <= a[1];
-			niili <= nii0l;
-			niill <= niili;
-			niilO <= nil1l;
-			niiO <= a[2];
-			niiOi <= nil1O;
-			niiOl <= nil0i;
-			niiOO <= nil0l;
-			nil0i <= a[12];
-			nil0l <= a[13];
-			nil0O <= a[14];
-			nil1i <= nil0O;
-			nil1l <= a[10];
-			nil1O <= a[11];
-			nili <= a[3];
-			nilii <= (nii0i & (~ niill));
-			nilil <= niliO;
-			niliO <= nilli;
-			nill <= wire_nii_dataout;
-			nilli <= a[15];
-			nilll <= nii1O;
-			nillO <= nilll;
-			nilOi <= nii1l;
-			nilOl <= (wire_nlO_o[6] & ((~ nii0i) & (~ nii1l)));
-			nilOO <= (nii0i & niill);
-			niO0i <= a[7];
-			niO0l <= a[8];
-			niO0O <= a[9];
-			niO1i <= a[4];
-			niO1l <= a[5];
-			niO1O <= a[6];
-			niOii <= wire_nlO1O_o[3];
-			niOil <= wire_nlO1O_o[4];
-			niOiO <= wire_nlO1O_o[5];
-			niOli <= wire_nlO1O_o[6];
-			niOll <= wire_nlO1O_o[7];
-			niOlO <= wire_nlO1O_o[8];
-			niOOi <= wire_nlO1O_o[9];
-			niOOl <= wire_nlO1O_o[10];
-			niOOO <= wire_nlO1O_o[11];
-			nl11i <= wire_nlO1O_o[12];
-			nl11l <= nillO;
-			nlO0i <= wire_nlOOO_o;
-			nlO0O <= wire_n11l_o;
-			nlO1l <= wire_nlOOl_o;
-			nlOii <= wire_n11O_o;
-			nlOil <= wire_n10i_o;
-			nlOiO <= wire_n10l_o;
-			nlOli <= wire_n10O_o;
-			nlOll <= wire_n1ii_o;
-			nlOlO <= wire_n1il_o;
-			nlOOi <= wire_n1OO_o;
-		end
-	end
-	assign
-		wire_n0l_ENA = en[0];
-	initial
-	begin
-		n1Oi = 0;
-		nlO0l = 0;
-	end
-	always @ ( posedge clk or  posedge areset)
-	begin
-		if (areset == 1'b1) 
-		begin
-			n1Oi <= 1;
-			nlO0l <= 1;
-		end
-		else if  (wire_n1lO_ENA == 1'b1) 
-		begin
-			n1Oi <= wire_n00i_o;
-			nlO0l <= wire_n11i_o;
-		end
-	end
-	assign
-		wire_n1lO_ENA = en[0];
-	event n1Oi_event;
-	event nlO0l_event;
-	initial
-		#1 ->n1Oi_event;
-	initial
-		#1 ->nlO0l_event;
-	always @(n1Oi_event)
-		n1Oi <= 1;
-	always @(nlO0l_event)
-		nlO0l <= 1;
-	assign		wire_nii_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[1] : wire_ni_o[1];
-	assign		wire_nil_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[2] : wire_ni_o[2];
-	assign		wire_niO_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[3] : wire_ni_o[3];
-	assign		wire_nli_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[4] : wire_ni_o[4];
-	assign		wire_nll_dataout = ((~ nillO) === 1'b1) ? wire_nlO_o[5] : wire_ni_o[5];
-	and(wire_nllii_dataout, niOii, (~ nl11l));
-	and(wire_nllil_dataout, niOil, (~ nl11l));
-	and(wire_nlliO_dataout, niOiO, (~ nl11l));
-	and(wire_nllli_dataout, niOli, (~ nl11l));
-	and(wire_nllll_dataout, niOll, (~ nl11l));
-	and(wire_nlllO_dataout, niOlO, (~ nl11l));
-	and(wire_nllOi_dataout, niOOi, (~ nl11l));
-	and(wire_nllOl_dataout, niOOl, (~ nl11l));
-	and(wire_nllOO_dataout, niOOO, (~ nl11l));
-	and(wire_nlO1i_dataout, nl11i, (~ nl11l));
-	oper_add   ni
-	( 
-	.a({1'b1, (~ nil1i), (~ niiOO), (~ niiOl), (~ niiOi), (~ niilO), 1'b1}),
-	.b({1'b0, {4{1'b1}}, 1'b0, 1'b1}),
-	.cin(1'b0),
-	.cout(),
-	.o(wire_ni_o));
-	defparam
-		ni.sgate_representation = 0,
-		ni.width_a = 7,
-		ni.width_b = 7,
-		ni.width_o = 7;
-	oper_add   nlO
-	( 
-	.a({1'b1, (~ nil1i), (~ niiOO), (~ niiOl), (~ niiOi), (~ niilO), 1'b1}),
-	.b({1'b0, {3{1'b1}}, 1'b0, {2{1'b1}}}),
-	.cin(1'b0),
-	.cout(),
-	.o(wire_nlO_o));
-	defparam
-		nlO.sgate_representation = 0,
-		nlO.width_a = 7,
-		nlO.width_b = 7,
-		nlO.width_o = 7;
-	oper_add   nlO1O
-	( 
-	.a({{2{1'b0}}, n1Oi, n1ll, n1li, n1iO, nlOOi, nlOlO, nlOll, nlOli, nlOiO, nlOil, nlOii, nlO0O, nlO0l, nlO0i, nlO1l}),
-	.b({{9{n0lO}}, n0ll, n0li, n0iO, n0il, n0ii, n00O, n00l, n1Ol}),
-	.cin(1'b0),
-	.cout(),
-	.o(wire_nlO1O_o));
-	defparam
-		nlO1O.sgate_representation = 0,
-		nlO1O.width_a = 17,
-		nlO1O.width_b = 17,
-		nlO1O.width_o = 17;
-	oper_mult   nilO
-	( 
-	.a({1'b0, nili, niiO, niil, niii}),
-	.b({ni0O, ni0l, ni0i, ni1O, ni1l, ni1i, n0OO, n0Ol, n0Oi}),
-	.o(wire_nilO_o));
-	defparam
-		nilO.sgate_representation = 1,
-		nilO.width_a = 5,
-		nilO.width_b = 9,
-		nilO.width_o = 14;
-	oper_mux   n00i
-	( 
-	.data({{63{1'b0}}, 1'b1}),
-	.o(wire_n00i_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n00i.width_data = 64,
-		n00i.width_sel = 6;
-	oper_mux   n01i
-	( 
-	.data({{25{1'b0}}, {17{1'b1}}, {12{1'b0}}, {9{1'b1}}, 1'b0}),
-	.o(wire_n01i_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n01i.width_data = 64,
-		n01i.width_sel = 6;
-	oper_mux   n01l
-	( 
-	.data({{42{1'b0}}, {21{1'b1}}, 1'b0}),
-	.o(wire_n01l_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n01l.width_data = 64,
-		n01l.width_sel = 6;
-	oper_mux   n01O
-	( 
-	.data({{63{1'b1}}, 1'b0}),
-	.o(wire_n01O_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n01O.width_data = 64,
-		n01O.width_sel = 6;
-	oper_mux   n10i
-	( 
-	.data({{7{1'b0}}, {3{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {3{1'b1}}, {8{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {3{1'b1}}, 1'b0, {3{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, {3{1'b0}}}),
-	.o(wire_n10i_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n10i.width_data = 64,
-		n10i.width_sel = 6;
-	oper_mux   n10l
-	( 
-	.data({1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {3{1'b1}}, {13{1'b0}}, {3{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {4{1'b0}}}),
-	.o(wire_n10l_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n10l.width_data = 64,
-		n10l.width_sel = 6;
-	oper_mux   n10O
-	( 
-	.data({1'b0, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, {3{1'b1}}, {6{1'b0}}}),
-	.o(wire_n10O_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n10O.width_data = 64,
-		n10O.width_sel = 6;
-	oper_mux   n11i
-	( 
-	.data({{2{1'b1}}, 1'b0, 1'b1, 1'b0, {4{1'b1}}, 1'b0, 1'b1, {4{1'b0}}, 1'b1, {4{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, 1'b0, {10{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, {3{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}}),
-	.o(wire_n11i_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n11i.width_data = 64,
-		n11i.width_sel = 6;
-	oper_mux   n11l
-	( 
-	.data({{2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, {6{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {3{1'b1}}, {3{1'b0}}, 1'b1, {3{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {10{1'b0}}}),
-	.o(wire_n11l_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n11l.width_data = 64,
-		n11l.width_sel = 6;
-	oper_mux   n11O
-	( 
-	.data({{4{1'b0}}, {3{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {6{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, {6{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, {5{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, {4{1'b0}}, 1'b1, {2{1'b0}}}),
-	.o(wire_n11O_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n11O.width_data = 64,
-		n11O.width_sel = 6;
-	oper_mux   n1ii
-	( 
-	.data({{3{1'b0}}, {4{1'b1}}, {3{1'b0}}, {4{1'b1}}, {3{1'b0}}, {3{1'b1}}, {2{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0}),
-	.o(wire_n1ii_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n1ii.width_data = 64,
-		n1ii.width_sel = 6;
-	oper_mux   n1il
-	( 
-	.data({{7{1'b0}}, {7{1'b1}}, {6{1'b0}}, {5{1'b1}}, {5{1'b0}}, {4{1'b1}}, {4{1'b0}}, {4{1'b1}}, {4{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {3{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0}),
-	.o(wire_n1il_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n1il.width_data = 64,
-		n1il.width_sel = 6;
-	oper_mux   n1OO
-	( 
-	.data({{14{1'b0}}, {11{1'b1}}, {9{1'b0}}, {8{1'b1}}, {7{1'b0}}, {5{1'b1}}, {5{1'b0}}, {4{1'b1}}, 1'b0}),
-	.o(wire_n1OO_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		n1OO.width_data = 64,
-		n1OO.width_sel = 6;
-	oper_mux   niOi
-	( 
-	.data({{2{1'b0}}, {3{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, 1'b0, {4{1'b1}}, 1'b0, {2{1'b1}}, {7{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, {6{1'b0}}, {2{1'b1}}, 1'b0, {3{1'b1}}, {6{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {4{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1}),
-	.o(wire_niOi_o),
-	.sel({a[9:4]}));
-	defparam
-		niOi.width_data = 64,
-		niOi.width_sel = 6;
-	oper_mux   niOl
-	( 
-	.data({1'b0, 1'b1, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {5{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {6{1'b1}}, {3{1'b0}}, {2{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, 1'b0, 1'b1}),
-	.o(wire_niOl_o),
-	.sel({a[9:4]}));
-	defparam
-		niOl.width_data = 64,
-		niOl.width_sel = 6;
-	oper_mux   niOO
-	( 
-	.data({1'b0, {3{1'b1}}, {4{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {3{1'b0}}, {3{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, {4{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1, {2{1'b0}}, {2{1'b1}}, {3{1'b0}}, 1'b1, 1'b0}),
-	.o(wire_niOO_o),
-	.sel({a[9:4]}));
-	defparam
-		niOO.width_data = 64,
-		niOO.width_sel = 6;
-	oper_mux   nl0i
-	( 
-	.data({1'b1, {37{1'b0}}, {16{1'b1}}, {10{1'b0}}}),
-	.o(wire_nl0i_o),
-	.sel({a[9:4]}));
-	defparam
-		nl0i.width_data = 64,
-		nl0i.width_sel = 6;
-	oper_mux   nl0l
-	( 
-	.data({{19{1'b1}}, {13{1'b0}}}),
-	.o(wire_nl0l_o),
-	.sel({a[9:5]}));
-	defparam
-		nl0l.width_data = 32,
-		nl0l.width_sel = 5;
-	oper_mux   nl0O
-	( 
-	.data({{2{1'b1}}, nill, 1'b0}),
-	.o(wire_nl0O_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nl0O.width_data = 4,
-		nl0O.width_sel = 2;
-	oper_mux   nl1i
-	( 
-	.data({1'b0, {7{1'b1}}, {6{1'b0}}, {5{1'b1}}, {5{1'b0}}, {4{1'b1}}, {3{1'b0}}, {4{1'b1}}, {3{1'b0}}, {3{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0}),
-	.o(wire_nl1i_o),
-	.sel({a[9:4]}));
-	defparam
-		nl1i.width_data = 64,
-		nl1i.width_sel = 6;
-	oper_mux   nl1l
-	( 
-	.data({1'b0, {13{1'b1}}, {10{1'b0}}, {7{1'b1}}, {7{1'b0}}, {5{1'b1}}, {4{1'b0}}, {4{1'b1}}, {3{1'b0}}, {3{1'b1}}, {3{1'b0}}, {2{1'b1}}, {2{1'b0}}}),
-	.o(wire_nl1l_o),
-	.sel({a[9:4]}));
-	defparam
-		nl1l.width_data = 64,
-		nl1l.width_sel = 6;
-	oper_mux   nl1O
-	( 
-	.data({1'b0, {23{1'b1}}, {14{1'b0}}, {9{1'b1}}, {7{1'b0}}, {6{1'b1}}, {4{1'b0}}}),
-	.o(wire_nl1O_o),
-	.sel({a[9:4]}));
-	defparam
-		nl1O.width_data = 64,
-		nl1O.width_sel = 6;
-	oper_mux   nlii
-	( 
-	.data({{2{1'b1}}, n1l, 1'b0}),
-	.o(wire_nlii_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nlii.width_data = 4,
-		nlii.width_sel = 2;
-	oper_mux   nlil
-	( 
-	.data({{2{1'b1}}, n1O, 1'b0}),
-	.o(wire_nlil_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nlil.width_data = 4,
-		nlil.width_sel = 2;
-	oper_mux   nlilO
-	( 
-	.data({1'b1, 1'b0, wire_nllii_dataout, 1'b0}),
-	.o(wire_nlilO_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nlilO.width_data = 4,
-		nlilO.width_sel = 2;
-	oper_mux   nliO
-	( 
-	.data({{2{1'b1}}, n0i, 1'b0}),
-	.o(wire_nliO_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nliO.width_data = 4,
-		nliO.width_sel = 2;
-	oper_mux   nliOi
-	( 
-	.data({{2{1'b0}}, wire_nllil_dataout, 1'b0}),
-	.o(wire_nliOi_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nliOi.width_data = 4,
-		nliOi.width_sel = 2;
-	oper_mux   nliOl
-	( 
-	.data({{2{1'b0}}, wire_nlliO_dataout, 1'b0}),
-	.o(wire_nliOl_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nliOl.width_data = 4,
-		nliOl.width_sel = 2;
-	oper_mux   nliOO
-	( 
-	.data({{2{1'b0}}, wire_nllli_dataout, 1'b0}),
-	.o(wire_nliOO_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nliOO.width_data = 4,
-		nliOO.width_sel = 2;
-	oper_mux   nll0i
-	( 
-	.data({{2{1'b0}}, wire_nllOl_dataout, 1'b0}),
-	.o(wire_nll0i_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nll0i.width_data = 4,
-		nll0i.width_sel = 2;
-	oper_mux   nll0l
-	( 
-	.data({{2{1'b0}}, wire_nllOO_dataout, 1'b0}),
-	.o(wire_nll0l_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nll0l.width_data = 4,
-		nll0l.width_sel = 2;
-	oper_mux   nll0O
-	( 
-	.data({{2{1'b0}}, wire_nlO1i_dataout, 1'b0}),
-	.o(wire_nll0O_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nll0O.width_data = 4,
-		nll0O.width_sel = 2;
-	oper_mux   nll1i
-	( 
-	.data({{2{1'b0}}, wire_nllll_dataout, 1'b0}),
-	.o(wire_nll1i_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nll1i.width_data = 4,
-		nll1i.width_sel = 2;
-	oper_mux   nll1l
-	( 
-	.data({{2{1'b0}}, wire_nlllO_dataout, 1'b0}),
-	.o(wire_nll1l_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nll1l.width_data = 4,
-		nll1l.width_sel = 2;
-	oper_mux   nll1O
-	( 
-	.data({{2{1'b0}}, wire_nllOi_dataout, 1'b0}),
-	.o(wire_nll1O_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nll1O.width_data = 4,
-		nll1O.width_sel = 2;
-	oper_mux   nlli
-	( 
-	.data({{2{1'b1}}, n0O, 1'b0}),
-	.o(wire_nlli_o),
-	.sel({wire_nllO_o, wire_nlll_o}));
-	defparam
-		nlli.width_data = 4,
-		nlli.width_sel = 2;
-	oper_mux   nlll
-	( 
-	.data({{5{1'b1}}, {2{1'b0}}, 1'b1}),
-	.o(wire_nlll_o),
-	.sel({nilii, nilOi, nii0O}));
-	defparam
-		nlll.width_data = 8,
-		nlll.width_sel = 3;
-	oper_mux   nllO
-	( 
-	.data({{3{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}}),
-	.o(wire_nllO_o),
-	.sel({nilii, nilOi, nii0O}));
-	defparam
-		nllO.width_data = 8,
-		nllO.width_sel = 3;
-	oper_mux   nlOOl
-	( 
-	.data({{2{1'b0}}, 1'b1, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {2{1'b0}}, 1'b1, {11{1'b0}}, {7{1'b1}}, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {7{1'b1}}, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, {3{1'b0}}, {2{1'b1}}, 1'b0}),
-	.o(wire_nlOOl_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		nlOOl.width_data = 64,
-		nlOOl.width_sel = 6;
-	oper_mux   nlOOO
-	( 
-	.data({1'b0, 1'b1, {3{1'b0}}, {12{1'b1}}, {5{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, {2{1'b0}}, {2{1'b1}}, 1'b0, {2{1'b1}}, 1'b0, {4{1'b1}}, {3{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, 1'b0, {2{1'b1}}, {2{1'b0}}, 1'b1, 1'b0, 1'b1, 1'b0, 1'b1, {2{1'b0}}, {3{1'b1}}, 1'b0}),
-	.o(wire_nlOOO_o),
-	.sel({niO0O, niO0l, niO0i, niO1O, niO1l, niO1i}));
-	defparam
-		nlOOO.width_data = 64,
-		nlOOO.width_sel = 6;
-	assign
-		nii0i = ((((nil1i & niiOO) & niiOl) & niiOi) & niilO),
-		nii0l = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])),
-		nii0O = (nilOl | nilOO),
-		nii1l = (((((~ nil1i) & (~ niiOO)) & (~ niiOl)) & (~ niiOi)) & (~ niilO)),
-		nii1O = ((((((((((~ a[0]) & (~ a[1])) & (~ a[2])) & (~ a[3])) & (~ a[4])) & (~ a[5])) & (~ a[6])) & (~ a[7])) & (~ a[8])) & (~ a[9])),
-		niiii = 1'b1,
-		q = {((~ nilii) & nilil), wire_nlli_o, wire_nliO_o, wire_nlil_o, wire_nlii_o, wire_nl0O_o, wire_nll0O_o, wire_nll0l_o, wire_nll0i_o, wire_nll1O_o, wire_nll1l_o, wire_nll1i_o, wire_nliOO_o, wire_nliOl_o, wire_nliOi_o, wire_nlilO_o};
-endmodule //ip_fp_inv
-//synopsys translate_on
-//VALID FILE
diff --git a/ip/ip_fp_inv_sim/mentor/msim_setup.tcl b/ip/ip_fp_inv_sim/mentor/msim_setup.tcl
deleted file mode 100644
index 933eae6..0000000
--- a/ip/ip_fp_inv_sim/mentor/msim_setup.tcl
+++ /dev/null
@@ -1,272 +0,0 @@
-
-# (C) 2001-2023 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ----------------------------------------
-# Auto-generated simulation script msim_setup.tcl
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     ip_fp_inv
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level script that compiles Altera simulation libraries and
-# the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "mentor.do", and modify the text as directed.
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator.
-# #
-# set QSYS_SIMDIR <script generation output directory>
-# #
-# # Source the generated IP simulation script.
-# source $QSYS_SIMDIR/mentor/msim_setup.tcl
-# #
-# # Set any compilation options you require (this is unusual).
-# set USER_DEFINED_COMPILE_OPTIONS <compilation options>
-# set USER_DEFINED_VHDL_COMPILE_OPTIONS <compilation options for VHDL>
-# set USER_DEFINED_VERILOG_COMPILE_OPTIONS <compilation options for Verilog>
-# #
-# # Call command to compile the Quartus EDA simulation library.
-# dev_com
-# #
-# # Call command to compile the Quartus-generated IP simulation files.
-# com
-# #
-# # Add commands to compile all design files and testbench files, including
-# # the top level. (These are all the files required for simulation other
-# # than the files compiled by the Quartus-generated IP simulation script)
-# #
-# vlog <compilation options> <design and testbench files>
-# #
-# # Set the top-level simulation or testbench module/entity name, which is
-# # used by the elab command to elaborate the top level.
-# #
-# set TOP_LEVEL_NAME <simulation top>
-# #
-# # Set any elaboration options you require.
-# set USER_DEFINED_ELAB_OPTIONS <elaboration options>
-# #
-# # Call command to elaborate your design and testbench.
-# elab
-# #
-# # Run the simulation.
-# run -a
-# #
-# # Report success to the shell.
-# exit -code 0
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If ip_fp_inv is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-
-# ----------------------------------------
-# Initialize variables
-if ![info exists SYSTEM_INSTANCE_NAME] { 
-  set SYSTEM_INSTANCE_NAME ""
-} elseif { ![ string match "" $SYSTEM_INSTANCE_NAME ] } { 
-  set SYSTEM_INSTANCE_NAME "/$SYSTEM_INSTANCE_NAME"
-}
-
-if ![info exists TOP_LEVEL_NAME] { 
-  set TOP_LEVEL_NAME "ip_fp_inv"
-}
-
-if ![info exists QSYS_SIMDIR] { 
-  set QSYS_SIMDIR "./../"
-}
-
-if ![info exists QUARTUS_INSTALL_DIR] { 
-  set QUARTUS_INSTALL_DIR "/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
-}
-
-if ![info exists USER_DEFINED_COMPILE_OPTIONS] { 
-  set USER_DEFINED_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VHDL_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VHDL_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_VERILOG_COMPILE_OPTIONS] { 
-  set USER_DEFINED_VERILOG_COMPILE_OPTIONS ""
-}
-if ![info exists USER_DEFINED_ELAB_OPTIONS] { 
-  set USER_DEFINED_ELAB_OPTIONS ""
-}
-
-# ----------------------------------------
-# Initialize simulation properties - DO NOT MODIFY!
-set ELAB_OPTIONS ""
-set SIM_OPTIONS ""
-if ![ string match "*-64 vsim*" [ vsim -version ] ] {
-} else {
-}
-
-# ----------------------------------------
-# Copy ROM/RAM files to simulation directory
-alias file_copy {
-  echo "\[exec\] file_copy"
-}
-
-# ----------------------------------------
-# Create compilation libraries
-proc ensure_lib { lib } { if ![file isdirectory $lib] { vlib $lib } }
-ensure_lib          ./libraries/     
-ensure_lib          ./libraries/work/
-vmap       work     ./libraries/work/
-vmap       work_lib ./libraries/work/
-if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
-  ensure_lib                       ./libraries/altera_ver/           
-  vmap       altera_ver            ./libraries/altera_ver/           
-  ensure_lib                       ./libraries/lpm_ver/              
-  vmap       lpm_ver               ./libraries/lpm_ver/              
-  ensure_lib                       ./libraries/sgate_ver/            
-  vmap       sgate_ver             ./libraries/sgate_ver/            
-  ensure_lib                       ./libraries/altera_mf_ver/        
-  vmap       altera_mf_ver         ./libraries/altera_mf_ver/        
-  ensure_lib                       ./libraries/altera_lnsim_ver/     
-  vmap       altera_lnsim_ver      ./libraries/altera_lnsim_ver/     
-  ensure_lib                       ./libraries/cyclonev_ver/         
-  vmap       cyclonev_ver          ./libraries/cyclonev_ver/         
-  ensure_lib                       ./libraries/cyclonev_hssi_ver/    
-  vmap       cyclonev_hssi_ver     ./libraries/cyclonev_hssi_ver/    
-  ensure_lib                       ./libraries/cyclonev_pcie_hip_ver/
-  vmap       cyclonev_pcie_hip_ver ./libraries/cyclonev_pcie_hip_ver/
-}
-
-
-# ----------------------------------------
-# Compile device library files
-alias dev_com {
-  echo "\[exec\] dev_com"
-  if ![ string match "*ModelSim ALTERA*" [ vsim -version ] ] {
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                     -work altera_ver           
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                              -work lpm_ver              
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                 -work sgate_ver            
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                             -work altera_mf_ver        
-    eval  vlog -sv $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                         -work altera_lnsim_ver     
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                        -work cyclonev_ver         
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                   -work cyclonev_hssi_ver    
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
-    eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS     "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"               -work cyclonev_pcie_hip_ver
-  }
-}
-
-# ----------------------------------------
-# Compile the design files in correct order
-alias com {
-  echo "\[exec\] com"
-  eval  vlog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
-}
-
-# ----------------------------------------
-# Elaborate top level design
-alias elab {
-  echo "\[exec\] elab"
-  eval vsim -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Elaborate the top level design with -voptargs=+acc option
-alias elab_debug {
-  echo "\[exec\] elab_debug"
-  eval vsim -voptargs=+acc -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cyclonev_ver -L cyclonev_hssi_ver -L cyclonev_pcie_hip_ver $TOP_LEVEL_NAME
-}
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design
-alias ld "
-  dev_com
-  com
-  elab
-"
-
-# ----------------------------------------
-# Compile all the design files and elaborate the top level design with -voptargs=+acc
-alias ld_debug "
-  dev_com
-  com
-  elab_debug
-"
-
-# ----------------------------------------
-# Print out user commmand line aliases
-alias h {
-  echo "List Of Command Line Aliases"
-  echo
-  echo "file_copy                                         -- Copy ROM/RAM files to simulation directory"
-  echo
-  echo "dev_com                                           -- Compile device library files"
-  echo
-  echo "com                                               -- Compile the design files in correct order"
-  echo
-  echo "elab                                              -- Elaborate top level design"
-  echo
-  echo "elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option"
-  echo
-  echo "ld                                                -- Compile all the design files and elaborate the top level design"
-  echo
-  echo "ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc"
-  echo
-  echo 
-  echo
-  echo "List Of Variables"
-  echo
-  echo "TOP_LEVEL_NAME                                    -- Top level module name."
-  echo "                                                     For most designs, this should be overridden"
-  echo "                                                     to enable the elab/elab_debug aliases."
-  echo
-  echo "SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module."
-  echo
-  echo "QSYS_SIMDIR                                       -- Platform Designer base simulation directory."
-  echo
-  echo "QUARTUS_INSTALL_DIR                               -- Quartus installation directory."
-  echo
-  echo "USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases."
-  echo
-  echo "USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases."
-  echo
-  echo "USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases."
-}
-file_copy
-h
diff --git a/ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh b/ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh
deleted file mode 100755
index a2444b0..0000000
--- a/ip/ip_fp_inv_sim/synopsys/vcs/vcs_setup.sh
+++ /dev/null
@@ -1,152 +0,0 @@
-
-# (C) 2001-2023 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-
-# ----------------------------------------
-# vcs - auto-generated simulation script
-
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     ip_fp_inv
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level shell script that compiles Altera simulation libraries
-# and the Quartus-generated IP in your project, along with your design and
-# testbench files, follow the guidelines below.
-# 
-# 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
-# below into a new file, e.g. named "vcs_sim.sh".
-# 
-# 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
-# a separate file, e.g. named "filelist.f".
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
-# # set the top-level simulation or testbench module/entity name.
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator.
-# #
-# # Source the Quartus-generated IP simulation script and do the following:
-# # - Compile the Quartus EDA simulation library and IP simulation files.
-# # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
-# # - Compile the design and top-level simulation module/entity using
-# #   information specified in "filelist.f".
-# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
-# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
-# # - Run the simulation.
-# #
-# source <script generation output directory>/synopsys/vcs/vcs_setup.sh \
-# TOP_LEVEL_NAME=<simulation top> \
-# QSYS_SIMDIR=<script generation output directory> \
-# USER_DEFINED_ELAB_OPTIONS="\"-f filelist.f\"" \
-# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# ----------------------------------------
-# # DESIGN FILE LIST & OPTIONS TEMPLATE - BEGIN
-# #
-# # Compile all design files and testbench files, including the top level.
-# # (These are all the files required for simulation other than the files
-# # compiled by the Quartus-generated IP simulation script)
-# #
-# +systemverilogext+.sv
-# <design and testbench files, compile-time options, elaboration options>
-# #
-# # DESIGN FILE LIST & OPTIONS TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If ip_fp_inv is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-# ----------------------------------------
-# initialize variables
-TOP_LEVEL_NAME="ip_fp_inv"
-QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
-SKIP_FILE_COPY=0
-SKIP_SIM=0
-USER_DEFINED_ELAB_OPTIONS=""
-USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
-# ----------------------------------------
-# overwrite variables - DO NOT MODIFY!
-# This block evaluates each command line argument, typically used for 
-# overwriting variables. An example usage:
-#   sh <simulator>_setup.sh SKIP_SIM=1
-for expression in "$@"; do
-  eval $expression
-  if [ $? -ne 0 ]; then
-    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
-    exit $?
-  fi
-done
-
-# ----------------------------------------
-# initialize simulation properties - DO NOT MODIFY!
-ELAB_OPTIONS=""
-SIM_OPTIONS=""
-if [[ `vcs -platform` != *"amd64"* ]]; then
-  :
-else
-  :
-fi
-
-# ----------------------------------------
-# copy RAM/ROM files to simulation directory
-
-vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v -ntb_opts dtm $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
-  $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v \
-  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v \
-  $QSYS_SIMDIR/ip_fp_inv.vo \
-  -top $TOP_LEVEL_NAME
-# ----------------------------------------
-# simulate
-if [ $SKIP_SIM -eq 0 ]; then
-  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
-fi
diff --git a/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup b/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup
deleted file mode 100644
index 5ae9b46..0000000
--- a/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup
+++ /dev/null
@@ -1,13 +0,0 @@
-
-WORK > DEFAULT
-DEFAULT:               ./libraries/work/                 
-work:                  ./libraries/work/                 
-altera_ver:            ./libraries/altera_ver/           
-lpm_ver:               ./libraries/lpm_ver/              
-sgate_ver:             ./libraries/sgate_ver/            
-altera_mf_ver:         ./libraries/altera_mf_ver/        
-altera_lnsim_ver:      ./libraries/altera_lnsim_ver/     
-cyclonev_ver:          ./libraries/cyclonev_ver/         
-cyclonev_hssi_ver:     ./libraries/cyclonev_hssi_ver/    
-cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/
-LIBRARY_SCAN = TRUE
diff --git a/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh
deleted file mode 100755
index f644e44..0000000
--- a/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh
+++ /dev/null
@@ -1,195 +0,0 @@
-
-# (C) 2001-2023 Altera Corporation. All rights reserved.
-# Your use of Altera Corporation's design tools, logic functions and 
-# other software and tools, and its AMPP partner logic functions, and 
-# any output files any of the foregoing (including device programming 
-# or simulation files), and any associated documentation or information 
-# are expressly subject to the terms and conditions of the Altera 
-# Program License Subscription Agreement, Altera MegaCore Function 
-# License Agreement, or other applicable license agreement, including, 
-# without limitation, that your use is for the sole purpose of 
-# programming logic devices manufactured by Altera and sold by Altera 
-# or its authorized distributors. Please refer to the applicable 
-# agreement for further details.
-
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-
-# ----------------------------------------
-# vcsmx - auto-generated simulation script
-
-# ----------------------------------------
-# This script provides commands to simulate the following IP detected in
-# your Quartus project:
-#     ip_fp_inv
-# 
-# Altera recommends that you source this Quartus-generated IP simulation
-# script from your own customized top-level script, and avoid editing this
-# generated script.
-# 
-# To write a top-level shell script that compiles Altera simulation libraries 
-# and the Quartus-generated IP in your project, along with your design and
-# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below
-# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed.
-# 
-# You can also modify the simulation flow to suit your needs. Set the
-# following variables to 1 to disable their corresponding processes:
-# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files
-# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library
-# - SKIP_COM: skip compiling Quartus-generated IP simulation files
-# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation
-# 
-# ----------------------------------------
-# # TOP-LEVEL TEMPLATE - BEGIN
-# #
-# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
-# # construct paths to the files required to simulate the IP in your Quartus
-# # project. By default, the IP script assumes that you are launching the
-# # simulator from the IP script location. If launching from another
-# # location, set QSYS_SIMDIR to the output directory you specified when you
-# # generated the IP script, relative to the directory from which you launch
-# # the simulator. In this case, you must also copy the generated library
-# # setup "synopsys_sim.setup" into the location from which you launch the
-# # simulator, or incorporate into any existing library setup.
-# #
-# # Run Quartus-generated IP simulation script once to compile Quartus EDA
-# # simulation libraries and Quartus-generated IP simulation files, and copy
-# # any ROM/RAM initialization files to the simulation directory.
-# #
-# # - If necessary, specify any compilation options:
-# #   USER_DEFINED_COMPILE_OPTIONS
-# #   USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler
-# #   USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler
-# #
-# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
-# SKIP_ELAB=1 \
-# SKIP_SIM=1 \
-# USER_DEFINED_COMPILE_OPTIONS=<compilation options for your design> \
-# USER_DEFINED_VHDL_COMPILE_OPTIONS=<VHDL compilation options for your design> \
-# USER_DEFINED_VERILOG_COMPILE_OPTIONS=<Verilog compilation options for your design> \
-# QSYS_SIMDIR=<script generation output directory>
-# #
-# # Compile all design files and testbench files, including the top level.
-# # (These are all the files required for simulation other than the files
-# # compiled by the IP script)
-# #
-# vlogan <compilation options> <design and testbench files>
-# #
-# # TOP_LEVEL_NAME is used in this script to set the top-level simulation or
-# # testbench module/entity name.
-# #
-# # Run the IP script again to elaborate and simulate the top level:
-# # - Specify TOP_LEVEL_NAME and USER_DEFINED_ELAB_OPTIONS.
-# # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
-# #   until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
-# #
-# source <script generation output directory>/synopsys/vcsmx/vcsmx_setup.sh \
-# SKIP_FILE_COPY=1 \
-# SKIP_DEV_COM=1 \
-# SKIP_COM=1 \
-# TOP_LEVEL_NAME="'-top <simulation top>'" \
-# QSYS_SIMDIR=<script generation output directory> \
-# USER_DEFINED_ELAB_OPTIONS=<elaboration options for your design> \
-# USER_DEFINED_SIM_OPTIONS=<simulation options for your design>
-# #
-# # TOP-LEVEL TEMPLATE - END
-# ----------------------------------------
-# 
-# IP SIMULATION SCRIPT
-# ----------------------------------------
-# If ip_fp_inv is one of several IP cores in your
-# Quartus project, you can generate a simulation script
-# suitable for inclusion in your top-level simulation
-# script by running the following command line:
-# 
-# ip-setup-simulation --quartus-project=<quartus project>
-# 
-# ip-setup-simulation will discover the Altera IP
-# within the Quartus project, and generate a unified
-# script which supports all the Altera IP within the design.
-# ----------------------------------------
-# ACDS 20.1 720 linux 2023.10.31.13:44:11
-# ----------------------------------------
-# initialize variables
-TOP_LEVEL_NAME="ip_fp_inv"
-QSYS_SIMDIR="./../../"
-QUARTUS_INSTALL_DIR="/nix/store/q54w47mfmcj9ag8kxwqvyi0snainbhjw-quartus-prime-lite-unwrapped-20.1.1.720/quartus/"
-SKIP_FILE_COPY=0
-SKIP_DEV_COM=0
-SKIP_COM=0
-SKIP_ELAB=0
-SKIP_SIM=0
-USER_DEFINED_ELAB_OPTIONS=""
-USER_DEFINED_SIM_OPTIONS="+vcs+finish+100"
-
-# ----------------------------------------
-# overwrite variables - DO NOT MODIFY!
-# This block evaluates each command line argument, typically used for 
-# overwriting variables. An example usage:
-#   sh <simulator>_setup.sh SKIP_SIM=1
-for expression in "$@"; do
-  eval $expression
-  if [ $? -ne 0 ]; then
-    echo "Error: This command line argument, \"$expression\", is/has an invalid expression." >&2
-    exit $?
-  fi
-done
-
-# ----------------------------------------
-# initialize simulation properties - DO NOT MODIFY!
-ELAB_OPTIONS=""
-SIM_OPTIONS=""
-if [[ `vcs -platform` != *"amd64"* ]]; then
-  :
-else
-  :
-fi
-
-# ----------------------------------------
-# create compilation libraries
-mkdir -p ./libraries/work/
-mkdir -p ./libraries/altera_ver/
-mkdir -p ./libraries/lpm_ver/
-mkdir -p ./libraries/sgate_ver/
-mkdir -p ./libraries/altera_mf_ver/
-mkdir -p ./libraries/altera_lnsim_ver/
-mkdir -p ./libraries/cyclonev_ver/
-mkdir -p ./libraries/cyclonev_hssi_ver/
-mkdir -p ./libraries/cyclonev_pcie_hip_ver/
-
-# ----------------------------------------
-# copy RAM/ROM files to simulation directory
-
-# ----------------------------------------
-# compile device library files
-if [ $SKIP_DEV_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v"                       -work altera_ver           
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v"                                -work lpm_ver              
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v"                                   -work sgate_ver            
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v"                               -work altera_mf_ver        
-  vlogan +v2k -sverilog $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv"                           -work altera_lnsim_ver     
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_atoms_ncrypt.v"          -work cyclonev_ver         
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hmi_atoms_ncrypt.v"      -work cyclonev_ver         
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_atoms.v"                          -work cyclonev_ver         
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_hssi_atoms_ncrypt.v"     -work cyclonev_hssi_ver    
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_hssi_atoms.v"                     -work cyclonev_hssi_ver    
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/cyclonev_pcie_hip_atoms_ncrypt.v" -work cyclonev_pcie_hip_ver
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS           "$QUARTUS_INSTALL_DIR/eda/sim_lib/cyclonev_pcie_hip_atoms.v"                 -work cyclonev_pcie_hip_ver
-fi
-
-# ----------------------------------------
-# compile design files in correct order
-if [ $SKIP_COM -eq 0 ]; then
-  vlogan +v2k $USER_DEFINED_VERILOG_COMPILE_OPTIONS $USER_DEFINED_COMPILE_OPTIONS "$QSYS_SIMDIR/ip_fp_inv.vo"
-fi
-
-# ----------------------------------------
-# elaborate top level design
-if [ $SKIP_ELAB -eq 0 ]; then
-  vcs -lca -t ps $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS $TOP_LEVEL_NAME
-fi
-
-# ----------------------------------------
-# simulate
-if [ $SKIP_SIM -eq 0 ]; then
-  ./simv $SIM_OPTIONS $USER_DEFINED_SIM_OPTIONS
-fi
-- 
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