From c2ddefda2ed6badddac5c229f59fcb25860759a4 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Mon, 20 Nov 2023 18:47:55 -0600 Subject: rtl/gfx: remove gfx_{perspective{,_flow}, fp_inv} --- ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup | 13 -- ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh | 195 --------------------- 2 files changed, 208 deletions(-) delete mode 100644 ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup delete mode 100755 ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh (limited to 'ip/ip_fp_inv_sim/synopsys/vcsmx') diff --git a/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup b/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup deleted file mode 100644 index 5ae9b46..0000000 --- a/ip/ip_fp_inv_sim/synopsys/vcsmx/synopsys_sim.setup +++ /dev/null @@ -1,13 +0,0 @@ - -WORK > DEFAULT -DEFAULT: ./libraries/work/ -work: ./libraries/work/ -altera_ver: ./libraries/altera_ver/ -lpm_ver: ./libraries/lpm_ver/ -sgate_ver: ./libraries/sgate_ver/ -altera_mf_ver: ./libraries/altera_mf_ver/ -altera_lnsim_ver: ./libraries/altera_lnsim_ver/ -cyclonev_ver: ./libraries/cyclonev_ver/ -cyclonev_hssi_ver: ./libraries/cyclonev_hssi_ver/ -cyclonev_pcie_hip_ver: ./libraries/cyclonev_pcie_hip_ver/ -LIBRARY_SCAN = TRUE diff --git a/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh b/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh deleted file mode 100755 index f644e44..0000000 --- a/ip/ip_fp_inv_sim/synopsys/vcsmx/vcsmx_setup.sh +++ /dev/null @@ -1,195 +0,0 @@ - -# (C) 2001-2023 Altera Corporation. All rights reserved. -# Your use of Altera Corporation's design tools, logic functions and -# other software and tools, and its AMPP partner logic functions, and -# any output files any of the foregoing (including device programming -# or simulation files), and any associated documentation or information -# are expressly subject to the terms and conditions of the Altera -# Program License Subscription Agreement, Altera MegaCore Function -# License Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by Altera -# or its authorized distributors. Please refer to the applicable -# agreement for further details. - -# ACDS 20.1 720 linux 2023.10.31.13:44:11 - -# ---------------------------------------- -# vcsmx - auto-generated simulation script - -# ---------------------------------------- -# This script provides commands to simulate the following IP detected in -# your Quartus project: -# ip_fp_inv -# -# Altera recommends that you source this Quartus-generated IP simulation -# script from your own customized top-level script, and avoid editing this -# generated script. -# -# To write a top-level shell script that compiles Altera simulation libraries -# and the Quartus-generated IP in your project, along with your design and -# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below -# into a new file, e.g. named "vcsmx_sim.sh", and modify text as directed. -# -# You can also modify the simulation flow to suit your needs. Set the -# following variables to 1 to disable their corresponding processes: -# - SKIP_FILE_COPY: skip copying ROM/RAM initialization files -# - SKIP_DEV_COM: skip compiling the Quartus EDA simulation library -# - SKIP_COM: skip compiling Quartus-generated IP simulation files -# - SKIP_ELAB and SKIP_SIM: skip elaboration and simulation -# -# ---------------------------------------- -# # TOP-LEVEL TEMPLATE - BEGIN -# # -# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to -# # construct paths to the files required to simulate the IP in your Quartus -# # project. By default, the IP script assumes that you are launching the -# # simulator from the IP script location. If launching from another -# # location, set QSYS_SIMDIR to the output directory you specified when you -# # generated the IP script, relative to the directory from which you launch -# # the simulator. In this case, you must also copy the generated library -# # setup "synopsys_sim.setup" into the location from which you launch the -# # simulator, or incorporate into any existing library setup. -# # -# # Run Quartus-generated IP simulation script once to compile Quartus EDA -# # simulation libraries and Quartus-generated IP simulation files, and copy -# # any ROM/RAM initialization files to the simulation directory. -# # -# # - If necessary, specify any compilation options: -# # USER_DEFINED_COMPILE_OPTIONS -# # USER_DEFINED_VHDL_COMPILE_OPTIONS applied to vhdl compiler -# # USER_DEFINED_VERILOG_COMPILE_OPTIONS applied to verilog compiler -# # -# source