From 986863efed48dfba23907400beb7e5f025b75b50 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Thu, 26 Oct 2023 01:33:00 -0600 Subject: rtl/gfx: synchronize clock with SDRAM --- ip/ip_fp_add_sim/mentor/msim_setup.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'ip/ip_fp_add_sim/mentor') diff --git a/ip/ip_fp_add_sim/mentor/msim_setup.tcl b/ip/ip_fp_add_sim/mentor/msim_setup.tcl index 3cc824c..38204c6 100644 --- a/ip/ip_fp_add_sim/mentor/msim_setup.tcl +++ b/ip/ip_fp_add_sim/mentor/msim_setup.tcl @@ -94,7 +94,7 @@ # within the Quartus project, and generate a unified # script which supports all the Altera IP within the design. # ---------------------------------------- -# ACDS 20.1 720 linux 2023.10.21.20:34:02 +# ACDS 20.1 720 linux 2023.10.26.05:46:14 # ---------------------------------------- # Initialize variables -- cgit v1.2.3