From ce34e3dfb0fc38a5763f5b81360f35e6e880df91 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 19 Nov 2023 20:54:04 -0600 Subject: rtl/gfx: factor FIFO overflow logic --- gfx_hw.tcl | 1 + 1 file changed, 1 insertion(+) (limited to 'gfx_hw.tcl') diff --git a/gfx_hw.tcl b/gfx_hw.tcl index 6d00c4d..5c95186 100644 --- a/gfx_hw.tcl +++ b/gfx_hw.tcl @@ -79,6 +79,7 @@ add_fileset_file gfx_frag_bary.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_frag_bary.sv add_fileset_file gfx_frag_shade.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_frag_shade.sv add_fileset_file gfx_rop.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_rop.sv add_fileset_file gfx_fifo.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fifo.sv +add_fileset_file gfx_fifo_overflow.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_fifo_overflow.sv add_fileset_file gfx_mem.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_mem.sv add_fileset_file gfx_sp.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp.sv add_fileset_file gfx_sp_batch.sv SYSTEM_VERILOG PATH rtl/gfx/gfx_sp_batch.sv -- cgit v1.2.3