From bc98bc905c2e796f0d587719196f7e4bf344510a Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Fri, 29 Sep 2023 19:50:01 -0600 Subject: platform: add CPUs and caches to qsys --- core_hw.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'core_hw.tcl') diff --git a/core_hw.tcl b/core_hw.tcl index 852e6c5..93b6def 100644 --- a/core_hw.tcl +++ b/core_hw.tcl @@ -66,7 +66,7 @@ add_fileset_file writeback.sv SYSTEM_VERILOG PATH rtl/core/control/writeback.sv add_fileset_file ldst.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/ldst.sv add_fileset_file pop.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/pop.sv add_fileset_file sizes.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/sizes.sv -add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache.sv +add_fileset_file cache_ops.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_ops.sv add_fileset_file cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_lockdown.sv add_fileset_file cp15.sv SYSTEM_VERILOG PATH rtl/core/cp15/cp15.sv add_fileset_file cpuid.sv SYSTEM_VERILOG PATH rtl/core/cp15/cpuid.sv -- cgit v1.2.3