From f6929f9a4703e3eee9d7bd9752de055729cdd498 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 8 Nov 2022 13:00:40 -0600 Subject: Register decode output in a new porch stage --- conspiracion.qsf | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'conspiracion.qsf') diff --git a/conspiracion.qsf b/conspiracion.qsf index e5d1534..fdba1f9 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -153,7 +153,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cp15.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cpuid.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/map.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/coproc.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv @@ -171,6 +170,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mul.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/conds.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/porch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv @@ -278,4 +279,5 @@ set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION set_global_assignment -name QIP_FILE ip/dsp_mul.qip set_global_assignment -name SIP_FILE ip/dsp_mul.sip + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- cgit v1.2.3