From 986863efed48dfba23907400beb7e5f025b75b50 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Thu, 26 Oct 2023 01:33:00 -0600
Subject: rtl/gfx: synchronize clock with SDRAM

---
 conspiracion.qsf | 1 +
 1 file changed, 1 insertion(+)

(limited to 'conspiracion.qsf')

diff --git a/conspiracion.qsf b/conspiracion.qsf
index 4b3f531..f24575e 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -320,6 +320,7 @@ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_
 set_global_assignment -name QIP_FILE ip/ip_fp_mul.qip
 set_global_assignment -name SIP_FILE ip/ip_fp_mul.sip
 
+
 set_global_assignment -name QIP_FILE ip/ip_fp_add.qip
 set_global_assignment -name SIP_FILE ip/ip_fp_add.sip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
-- 
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