From 83be8cb319efc245c17512c86c494ace2ad022ff Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Fri, 23 Sep 2022 23:42:05 -0600 Subject: Add toplevel module for core tests --- conspiracion.qsf | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'conspiracion.qsf') diff --git a/conspiracion.qsf b/conspiracion.qsf index 850a26a..4242e25 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -56,8 +56,6 @@ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top -set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv -set_global_assignment -name QIP_FILE platform/synthesis/platform.qip set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_oct_rzqin -tag __hps_sdram_p0 set_instance_assignment -name IO_STANDARD "SSTL-15 CLASS I" -to memory_mem_dq[0] -tag __hps_sdram_p0 set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to memory_mem_dq[0] -tag __hps_sdram_p0 @@ -213,5 +211,15 @@ set_location_assignment PIN_Y21 -to done set_location_assignment PIN_AF14 -to clk_clk +set_global_assignment -name SEARCH_PATH rtl + +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv +set_global_assignment -name QSYS_FILE platform.qsys +set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv +set_global_assignment -name QIP_FILE platform/synthesis/platform.qip set_global_assignment -name SDC_FILE conspiracion.sdc + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- cgit v1.2.3