From 3aa075cf009d9aa8c602389853cc3ea78cda8701 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Sun, 25 Sep 2022 19:22:43 -0600 Subject: Fix Quartus issues --- conspiracion.qsf | 20 +++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) (limited to 'conspiracion.qsf') diff --git a/conspiracion.qsf b/conspiracion.qsf index 4242e25..c81ea0a 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -213,13 +213,31 @@ set_location_assignment PIN_AF14 -to clk_clk set_global_assignment -name SEARCH_PATH rtl -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/shifter.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/and.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/map.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/isa.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cycles.sv + set_global_assignment -name QSYS_FILE platform.qsys set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv set_global_assignment -name QIP_FILE platform/synthesis/platform.qip set_global_assignment -name SDC_FILE conspiracion.sdc + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file -- cgit v1.2.3