From 1b5eeb9a949272232ff543f684c7be62d31d0d40 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Fri, 20 Oct 2023 22:59:27 -0600
Subject: ip: add ip_fp_add, ip_fp_mul

---
 conspiracion.qsf | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'conspiracion.qsf')

diff --git a/conspiracion.qsf b/conspiracion.qsf
index 8a8ff81..4b3f531 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -317,4 +317,9 @@ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)
 set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
 
 
+set_global_assignment -name QIP_FILE ip/ip_fp_mul.qip
+set_global_assignment -name SIP_FILE ip/ip_fp_mul.sip
+
+set_global_assignment -name QIP_FILE ip/ip_fp_add.qip
+set_global_assignment -name SIP_FILE ip/ip_fp_add.sip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
-- 
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