From f786c0f2f6f00cab2203de4a672801ca9c179415 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Fri, 6 Oct 2023 16:41:15 -0600 Subject: tb: rename smp_sim to test_smp --- Makefile | 8 ++++---- rtl/top/smp_sim.sv | 36 ------------------------------------ rtl/top/test_smp.sv | 36 ++++++++++++++++++++++++++++++++++++ tb/top/smp_sim.cpp | 1 - tb/top/smp_sim.py | 43 ------------------------------------------- tb/top/test_smp.py | 43 +++++++++++++++++++++++++++++++++++++++++++ 6 files changed, 83 insertions(+), 84 deletions(-) delete mode 100644 rtl/top/smp_sim.sv create mode 100644 rtl/top/test_smp.sv delete mode 100644 tb/top/smp_sim.cpp delete mode 100644 tb/top/smp_sim.py create mode 100644 tb/top/test_smp.py diff --git a/Makefile b/Makefile index f9aa42f..c383b3e 100644 --- a/Makefile +++ b/Makefile @@ -15,7 +15,6 @@ RBF_OUT_DIR := output_files VERILATOR ?= verilator COCOTB_CONFIG ?= cocotb-config GENHTML ?= genhtml -COCOTB_CONFIG ?= cocotb-config CROSS_CC := $(CROSS_COMPILE)gcc CROSS_OBJCOPY := $(CROSS_COMPILE)objcopy CROSS_CFLAGS := -O3 -Wall -Wextra -Werror @@ -56,7 +55,7 @@ VFLAGS ?= \ VFLAGS += -O3 --cc --exe -y $(RTL_DIR) --prefix Vtop -LIBPYTHON = $(shell $(COCOTB_CONFIG) --libpython) +LIBPYTHON := $(shell $(COCOTB_CONFIG) --libpython) COCOTB_LDFLAGS := $(LDFLAGS) \ -Wl,-rpath,$(shell $(COCOTB_CONFIG) --lib-dir) \ @@ -180,7 +179,7 @@ exe/%: $(OBJ_DIR)/%/Vtop.mk @CXXFLAGS="$(CXXFLAGS) -iquote $(ROOT)/$(TB_DIR)/top/$*" \ $(MAKE) -C $(OBJ_DIR)/$* -f Vtop.mk -.PRECIOUS: $(OBJ_DIR)/%.mk $(SIM_OBJ_DIR)/% $(SIM_OBJ_DIR)/%.o $(SIM_OBJ_DIR)/%.cov %.bin +.PRECIOUS: $(OBJ_DIR)/%.mk $(SIM_OBJ_DIR)/% $(SIM_OBJ_DIR)/%.o $(SIM_OBJ_DIR)/%.cov %.bin $(FST_DIR)/% .PHONY: all clean dist demo sim .SECONDEXPANSION: @@ -188,7 +187,8 @@ exe/%: $(OBJ_DIR)/%/Vtop.mk $(OBJ_DIR)/%.mk: \ $(RTL_DIR)/top/$$(word 1,$$(subst /, ,$$*)).sv \ $$(shell find $(RTL_DIR)/top/$$(dir $$*) -type f 2>/dev/null) \ - $(RTL_FILES) $(TB_FILES) $(TB_DIR)/top/$$(word 1,$$(subst /, ,$$*)).cpp \ + $(RTL_FILES) $(TB_FILES) \ + $$(shell find $(TB_DIR)/top/$$(word 1,$$(subst /, ,$$*)).cpp -type f 2>/dev/null) \ $$(shell find $(TB_DIR)/top/$$(dir $$*) -type f 2>/dev/null) mkdir -p $(dir $@) diff --git a/rtl/top/smp_sim.sv b/rtl/top/smp_sim.sv deleted file mode 100644 index ff4d8a1..0000000 --- a/rtl/top/smp_sim.sv +++ /dev/null @@ -1,36 +0,0 @@ -module smp_sim -( - input logic clk, - rst_n, - - input logic avl_address, // No se usa, pero cocotb_bus lo requiere - avl_read, - avl_write, - input logic[31:0] avl_writedata, - output logic[31:0] avl_readdata, - - input logic cpu_halted_0, - cpu_halted_1, - cpu_halted_2, - cpu_halted_3, - input logic breakpoint_0, - breakpoint_1, - breakpoint_2, - breakpoint_3, - - output logic halt_0, - halt_1, - halt_2, - halt_3, - step_0, - step_1, - step_2, - step_3 -); - - smp_ctrl dut - ( - .* - ); - -endmodule diff --git a/rtl/top/test_smp.sv b/rtl/top/test_smp.sv new file mode 100644 index 0000000..df417c3 --- /dev/null +++ b/rtl/top/test_smp.sv @@ -0,0 +1,36 @@ +module test_smp +( + input logic clk, + rst_n, + + input logic avl_address, // No se usa, pero cocotb_bus lo requiere + avl_read, + avl_write, + input logic[31:0] avl_writedata, + output logic[31:0] avl_readdata, + + input logic cpu_halted_0, + cpu_halted_1, + cpu_halted_2, + cpu_halted_3, + input logic breakpoint_0, + breakpoint_1, + breakpoint_2, + breakpoint_3, + + output logic halt_0, + halt_1, + halt_2, + halt_3, + step_0, + step_1, + step_2, + step_3 +); + + smp_ctrl dut + ( + .* + ); + +endmodule diff --git a/tb/top/smp_sim.cpp b/tb/top/smp_sim.cpp deleted file mode 100644 index 4b58019..0000000 --- a/tb/top/smp_sim.cpp +++ /dev/null @@ -1 +0,0 @@ -// No necesitamos nada aquí, todo lo genera verilator+cocotb diff --git a/tb/top/smp_sim.py b/tb/top/smp_sim.py deleted file mode 100644 index 1994da2..0000000 --- a/tb/top/smp_sim.py +++ /dev/null @@ -1,43 +0,0 @@ -import cocotb -from cocotb.clock import Clock -from cocotb.triggers import Combine, ClockCycles, RisingEdge, Timer, with_timeout -from cocotb_bus.drivers.avalon import AvalonMaster - -from tb.models import CorePaceModel, SmpModel - -@cocotb.test() -async def reset(dut): - dut.rst_n.value = 1 - await Timer(1) - dut.rst_n.value = 0 - await Timer(1) - dut.rst_n.value = 1 - - model = SmpModel() - - cocotb.start_soon(Clock(dut.clk, 2).start()) - master = AvalonMaster(dut, 'avl', dut.clk, case_insensitive=False) - - cpu0 = CorePaceModel(clk=dut.clk, halt=dut.halt_0, step=dut.step_0, - bkpt=dut.breakpoint_0, halted=dut.cpu_halted_0) - - cpu1 = CorePaceModel(clk=dut.clk, halt=dut.halt_1, step=dut.step_1, - bkpt=dut.breakpoint_1, halted=dut.cpu_halted_1) - - cpu2 = CorePaceModel(clk=dut.clk, halt=dut.halt_2, step=dut.step_2, - bkpt=dut.breakpoint_2, halted=dut.cpu_halted_2) - - cpu3 = CorePaceModel(clk=dut.clk, halt=dut.halt_3, step=dut.step_3, - bkpt=dut.breakpoint_3, halted=dut.cpu_halted_3) - - cocotb.start_soon(cpu0.run()) - cocotb.start_soon(cpu1.run()) - cocotb.start_soon(cpu2.run()) - cocotb.start_soon(cpu3.run()) - - await with_timeout(Combine(*(RisingEdge(halted) for halted in - [dut.cpu_halted_1, dut.cpu_halted_2, dut.cpu_halted_3])), - 50) - - await ClockCycles(dut.clk, 5) - assert await master.read(0) == model.read() diff --git a/tb/top/test_smp.py b/tb/top/test_smp.py new file mode 100644 index 0000000..1994da2 --- /dev/null +++ b/tb/top/test_smp.py @@ -0,0 +1,43 @@ +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import Combine, ClockCycles, RisingEdge, Timer, with_timeout +from cocotb_bus.drivers.avalon import AvalonMaster + +from tb.models import CorePaceModel, SmpModel + +@cocotb.test() +async def reset(dut): + dut.rst_n.value = 1 + await Timer(1) + dut.rst_n.value = 0 + await Timer(1) + dut.rst_n.value = 1 + + model = SmpModel() + + cocotb.start_soon(Clock(dut.clk, 2).start()) + master = AvalonMaster(dut, 'avl', dut.clk, case_insensitive=False) + + cpu0 = CorePaceModel(clk=dut.clk, halt=dut.halt_0, step=dut.step_0, + bkpt=dut.breakpoint_0, halted=dut.cpu_halted_0) + + cpu1 = CorePaceModel(clk=dut.clk, halt=dut.halt_1, step=dut.step_1, + bkpt=dut.breakpoint_1, halted=dut.cpu_halted_1) + + cpu2 = CorePaceModel(clk=dut.clk, halt=dut.halt_2, step=dut.step_2, + bkpt=dut.breakpoint_2, halted=dut.cpu_halted_2) + + cpu3 = CorePaceModel(clk=dut.clk, halt=dut.halt_3, step=dut.step_3, + bkpt=dut.breakpoint_3, halted=dut.cpu_halted_3) + + cocotb.start_soon(cpu0.run()) + cocotb.start_soon(cpu1.run()) + cocotb.start_soon(cpu2.run()) + cocotb.start_soon(cpu3.run()) + + await with_timeout(Combine(*(RisingEdge(halted) for halted in + [dut.cpu_halted_1, dut.cpu_halted_2, dut.cpu_halted_3])), + 50) + + await ClockCycles(dut.clk, 5) + assert await master.read(0) == model.read() -- cgit v1.2.3