From f6929f9a4703e3eee9d7bd9752de055729cdd498 Mon Sep 17 00:00:00 2001 From: Alejandro Soto Date: Tue, 8 Nov 2022 13:00:40 -0600 Subject: Register decode output in a new porch stage --- conspiracion.qsf | 4 +++- rtl/core/arm810.sv | 27 +++++++++++++++++------ rtl/core/control/control.sv | 2 +- rtl/core/control/issue.sv | 8 +++---- rtl/core/decode/conds.sv | 47 ---------------------------------------- rtl/core/decode/decode.sv | 12 ---------- rtl/core/decode/mux.sv | 16 +++++--------- rtl/core/fetch/fetch.sv | 14 ++++++------ rtl/core/porch/conds.sv | 47 ++++++++++++++++++++++++++++++++++++++++ rtl/core/porch/porch.sv | 53 +++++++++++++++++++++++++++++++++++++++++++++ 10 files changed, 141 insertions(+), 89 deletions(-) delete mode 100644 rtl/core/decode/conds.sv create mode 100644 rtl/core/porch/conds.sv create mode 100644 rtl/core/porch/porch.sv diff --git a/conspiracion.qsf b/conspiracion.qsf index e5d1534..fdba1f9 100644 --- a/conspiracion.qsf +++ b/conspiracion.qsf @@ -153,7 +153,6 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cp15.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cpuid.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/map.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/conds.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/coproc.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv @@ -171,6 +170,8 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mul.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/conds.sv +set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/porch.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv @@ -278,4 +279,5 @@ set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION set_global_assignment -name QIP_FILE ip/dsp_mul.qip set_global_assignment -name SIP_FILE ip/dsp_mul.sip + set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv index 3f2a53c..07a397b 100644 --- a/rtl/core/arm810.sv +++ b/rtl/core/arm810.sv @@ -13,25 +13,38 @@ module arm810 output word bus_data_wr ); - logic stall, prefetch_flush, insn_start; - word insn; ptr fetch_insn_pc, insn_addr; + word fetch_insn; + logic stall, flush, prefetch_flush, insn_start; + + //TODO + assign prefetch_flush = 0; core_fetch #(.PREFETCH_ORDER(2)) fetch ( - .branch(explicit_branch || wr_pc), - .flush(0), //TODO .addr(insn_addr), - .fetched(insn_ready), - .fetch_data(insn_data_rd), + .insn(fetch_insn), .fetch(insn_start), + .branch(explicit_branch || wr_pc), + .fetched(insn_ready), .insn_pc(fetch_insn_pc), + .fetch_data(insn_data_rd), .* ); - insn_decode dec; + insn_decode fetch_dec; core_decode decode + ( + .dec(fetch_dec), + .insn(fetch_insn) + ); + + ptr insn_pc; + word insn; + insn_decode dec; + + core_porch porch ( .* ); diff --git a/rtl/core/control/control.sv b/rtl/core/control/control.sv index 4ea590a..077ba1c 100644 --- a/rtl/core/control/control.sv +++ b/rtl/core/control/control.sv @@ -4,7 +4,7 @@ module core_control ( input logic clk, input insn_decode dec, - input ptr fetch_insn_pc, + input ptr insn_pc, input psr_flags flags, alu_flags, input word rd_value_a, diff --git a/rtl/core/control/issue.sv b/rtl/core/control/issue.sv index 5ed03f0..e3644c4 100644 --- a/rtl/core/control/issue.sv +++ b/rtl/core/control/issue.sv @@ -5,7 +5,7 @@ module core_control_issue input logic clk, input insn_decode dec, - input ptr fetch_insn_pc, + input ptr insn_pc, input ctrl_cycle next_cycle, input logic next_bubble, @@ -22,7 +22,7 @@ module core_control_issue ); assign issue = next_cycle == ISSUE && dec.ctrl.execute && !next_bubble; - assign next_pc_visible = fetch_insn_pc + 2; + assign next_pc_visible = insn_pc + 2; always_ff @(posedge clk) if(next_cycle == ISSUE) begin @@ -30,10 +30,10 @@ module core_control_issue `ifdef VERILATOR if(dec.ctrl.undefined) - $display("[core] undefined insn: [0x%08x] %08x", fetch_insn_pc << 2, insn); + $display("[core] undefined insn: [0x%08x] %08x", insn_pc << 2, insn); `endif - pc <= fetch_insn_pc; + pc <= insn_pc; pc_visible <= next_pc_visible; end diff --git a/rtl/core/decode/conds.sv b/rtl/core/decode/conds.sv deleted file mode 100644 index 60922a0..0000000 --- a/rtl/core/decode/conds.sv +++ /dev/null @@ -1,47 +0,0 @@ -`include "core/decode/isa.sv" -`include "core/uarch.sv" - -module core_decode_conds -( - input logic[3:0] cond, - input psr_flags flags, - - output logic execute, - conditional, - undefined -); - - always_comb begin - undefined = 0; - conditional = 1; - - unique case(cond) - `COND_EQ: execute = flags.z; - `COND_NE: execute = ~flags.z; - `COND_HS: execute = flags.c; - `COND_LO: execute = ~flags.c; - `COND_MI: execute = flags.n; - `COND_PL: execute = ~flags.n; - `COND_VS: execute = flags.v; - `COND_VC: execute = ~flags.v; - `COND_HI: execute = flags.c & ~flags.z; - `COND_LS: execute = ~flags.c | flags.z; - `COND_GE: execute = flags.n ~^ flags.v; - `COND_LT: execute = flags.n ^ flags.v; - `COND_GT: execute = ~flags.z & (flags.n ~^ flags.v); - `COND_LE: execute = flags.z | (flags.n ^ flags.v); - - `COND_AL: begin - execute = 1; - conditional = 0; - end - - `COND_UD: begin - execute = 1'bx; - conditional = 1'bx; - undefined = 1; - end - endcase - end - -endmodule diff --git a/rtl/core/decode/decode.sv b/rtl/core/decode/decode.sv index ab8d2b9..6c5b802 100644 --- a/rtl/core/decode/decode.sv +++ b/rtl/core/decode/decode.sv @@ -4,7 +4,6 @@ module core_decode ( input word insn, - input psr_flags flags, output insn_decode dec ); @@ -51,17 +50,6 @@ module core_decode //TODO logic restore_spsr; - logic cond_undefined, cond_execute, explicit_cond; - - core_decode_conds conds - ( - .cond(insn `FIELD_COND), - .execute(cond_execute), - .undefined(cond_undefined), - .conditional(explicit_cond), - .* - ); - logic snd_is_imm, snd_ror_if_imm, snd_shift_by_reg_if_reg, snd_undefined; snd_decode snd; diff --git a/rtl/core/decode/mux.sv b/rtl/core/decode/mux.sv index 643c942..ebcc098 100644 --- a/rtl/core/decode/mux.sv +++ b/rtl/core/decode/mux.sv @@ -5,10 +5,6 @@ module core_decode_mux ( input word insn, - input logic cond_undefined, - cond_execute, - explicit_cond, - input logic branch_link, input snd_decode snd, @@ -74,10 +70,10 @@ module core_decode_mux ldst = 0; branch = 0; coproc = 0; - execute = cond_execute; - undefined = cond_undefined; + execute = 1; + undefined = 0; writeback = 0; - conditional = explicit_cond; + conditional = 0; restore_spsr = 0; spsr = 0; @@ -139,8 +135,8 @@ module core_decode_mux update_flags = data_update_flags; restore_spsr = data_restore_spsr; - undefined = undefined | snd_undefined; - conditional = conditional | data_conditional; + undefined = snd_undefined; + conditional = data_conditional; end `GROUP_LDST_SINGLE_IMM, `GROUP_LDST_SINGLE_REG: begin @@ -152,7 +148,7 @@ module core_decode_mux dec_ldst = ldst_single; ldst_addr = ldst_single; - undefined = undefined | snd_undefined; + undefined = snd_undefined; end `GROUP_LDST_MISC_IMM, `GROUP_LDST_MISC_REG: diff --git a/rtl/core/fetch/fetch.sv b/rtl/core/fetch/fetch.sv index d938699..bb52443 100644 --- a/rtl/core/fetch/fetch.sv +++ b/rtl/core/fetch/fetch.sv @@ -6,29 +6,29 @@ module core_fetch input logic clk, stall, branch, - flush, fetched, wr_pc, + prefetch_flush, input ptr branch_target, input word wr_current, fetch_data, output logic fetch, + flush, output word insn, output ptr insn_pc, addr ); ptr next_pc, head, hold_addr, target; - logic fetched_valid, do_flush, discard; + logic fetched_valid, discard; + assign flush = branch || prefetch_flush; assign target = wr_pc ? wr_current[31:2] : branch_target; //TODO: alignment exception - assign do_flush = branch || flush; assign fetched_valid = fetched && !discard; core_prefetch #(.ORDER(PREFETCH_ORDER)) prefetch ( - .flush(do_flush), .fetched(fetched_valid), .* ); @@ -36,12 +36,12 @@ module core_fetch always_comb begin if(branch) head = target; - else if(flush) + else if(prefetch_flush) head = next_pc; else head = {30{1'bx}}; - if(do_flush) + if(flush) addr = head; else if(fetch && fetched_valid) addr = hold_addr + 1; @@ -50,7 +50,7 @@ module core_fetch end always_ff @(posedge clk) begin - discard <= discard ? ~fetched : do_flush & fetch; + discard <= discard ? !fetched : flush && fetch; hold_addr <= addr; end diff --git a/rtl/core/porch/conds.sv b/rtl/core/porch/conds.sv new file mode 100644 index 0000000..b8db1e7 --- /dev/null +++ b/rtl/core/porch/conds.sv @@ -0,0 +1,47 @@ +`include "core/decode/isa.sv" +`include "core/uarch.sv" + +module core_porch_conds +( + input word insn, + input psr_flags flags, + + output logic execute, + conditional, + undefined +); + + always_comb begin + undefined = 0; + conditional = 1; + + unique case(insn `FIELD_COND) + `COND_EQ: execute = flags.z; + `COND_NE: execute = ~flags.z; + `COND_HS: execute = flags.c; + `COND_LO: execute = ~flags.c; + `COND_MI: execute = flags.n; + `COND_PL: execute = ~flags.n; + `COND_VS: execute = flags.v; + `COND_VC: execute = ~flags.v; + `COND_HI: execute = flags.c & ~flags.z; + `COND_LS: execute = ~flags.c | flags.z; + `COND_GE: execute = flags.n ~^ flags.v; + `COND_LT: execute = flags.n ^ flags.v; + `COND_GT: execute = ~flags.z & (flags.n ~^ flags.v); + `COND_LE: execute = flags.z | (flags.n ^ flags.v); + + `COND_AL: begin + execute = 1; + conditional = 0; + end + + `COND_UD: begin + execute = 1'bx; + conditional = 1'bx; + undefined = 1; + end + endcase + end + +endmodule diff --git a/rtl/core/porch/porch.sv b/rtl/core/porch/porch.sv new file mode 100644 index 0000000..6f5caf7 --- /dev/null +++ b/rtl/core/porch/porch.sv @@ -0,0 +1,53 @@ +`include "core/uarch.sv" + +module core_porch +( + input logic clk, + flush, + stall, + input psr_flags flags, + + input word fetch_insn, + input ptr fetch_insn_pc, + input insn_decode fetch_dec, + + output word insn, + output ptr insn_pc, + output insn_decode dec +); + + logic execute, conditional, undefined; + insn_decode nop, hold_dec; + + core_porch_conds conds + ( + .* + ); + + assign nop.ctrl.execute = 0; + assign nop.ctrl.undefined = 0; + assign nop.ctrl.conditional = 0; + + always_comb begin + dec = hold_dec; + dec.ctrl.execute = !flush && dec.ctrl.execute && execute; + dec.ctrl.undefined = !flush && (dec.ctrl.undefined || undefined); + dec.ctrl.conditional = !flush && (dec.ctrl.conditional || conditional); + end + + always @(posedge clk) + if(!stall) begin + insn <= fetch_insn; + hold_dec <= fetch_dec; + + if(!flush) + insn_pc <= fetch_insn_pc; + end + + initial begin + insn = `NOP; + insn_pc = 0; + hold_dec = nop; + end + +endmodule -- cgit v1.2.3