From f65e5611fde5e1c3e3a509cb2f3ffcafce5bbd33 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Sun, 25 Sep 2022 17:47:38 -0600
Subject: Implement PSR flag handling

---
 rtl/core/arm810.sv | 25 +++++++++++++++++++------
 rtl/core/cycles.sv | 41 ++++++++++++++++++++++++++---------------
 2 files changed, 45 insertions(+), 21 deletions(-)

diff --git a/rtl/core/arm810.sv b/rtl/core/arm810.sv
index 82479d1..9a99168 100644
--- a/rtl/core/arm810.sv
+++ b/rtl/core/arm810.sv
@@ -17,9 +17,6 @@ module arm810
 	word insn;
 	ptr fetch_insn_pc, pc, pc_visible;
 
-	psr_flags flags;
-	assign flags = 4'b1010; //TODO
-
 	core_fetch #(.PREFETCH_ORDER(2)) fetch
 	(
 		.flush(explicit_branch | wr_pc),
@@ -35,15 +32,18 @@ module arm810
 	logic decode_execute, decode_undefined, decode_writeback, decode_branch;
 	ptr decode_branch_offset;
 	reg_num decode_rd;
+	alu_op decode_data_op;
 
 	core_decode decode
 	(
+		.flags(next_flags),
 		.execute(decode_execute),
 		.undefined(decode_undefined),
 		.writeback(decode_writeback),
 		.rd(decode_rd),
 		.branch(decode_branch),
 		.branch_offset(decode_branch_offset),
+		.data_op(decode_data_op),
 		.*
 	);
 
@@ -51,6 +51,8 @@ module arm810
 	logic explicit_branch, writeback;
 	ptr branch_target;
 	psr_mode reg_mode;
+	alu_op data_op;
+	psr_flags flags, next_flags;
 
 	core_cycles cycles
 	(
@@ -59,14 +61,12 @@ module arm810
 	);
 
 	logic wr_pc;
-	word wr_value;
+	word wr_value, rd_value_a, rd_value_b;
 
 	core_regs regs
 	(
 		.rd_r_a(0), //TODO
 		.rd_r_b(0), //TODO
-		.rd_value_a(), //TODO
-		.rd_value_b(), //TODO
 		.rd_mode(reg_mode),
 		.wr_mode(reg_mode),
 		.wr_r(rd),
@@ -75,4 +75,17 @@ module arm810
 		.*
 	);
 
+	psr_flags alu_flags;
+
+	core_alu #(.W(32)) alu
+	(
+		.op(data_op),
+		.a(rd_value_a),
+		.b(rd_value_b),
+		.c_in(flags.c),
+		.q(wr_value),
+		.nzcv(alu_flags),
+		.v_valid() //TODO
+	);
+
 endmodule
diff --git a/rtl/core/cycles.sv b/rtl/core/cycles.sv
index 64d77e6..d52c0b0 100644
--- a/rtl/core/cycles.sv
+++ b/rtl/core/cycles.sv
@@ -1,22 +1,29 @@
+`include "core/psr.sv"
 `include "core/uarch.sv"
 
 module core_cycles
 (
-	input  logic    clk,
-	                decode_execute,
-	                decode_writeback,
-	                decode_branch,
-	input  ptr      decode_branch_offset,
-	input  reg_num  decode_rd,
-	input  ptr      fetch_insn_pc,
-
-	output logic    stall,
-	                branch,
-	                writeback,
-	output ptr      branch_target,
-	                pc,
-	                pc_visible,
-	output psr_mode reg_mode
+	input  logic     clk,
+	                 decode_execute,
+	                 decode_writeback,
+	                 decode_branch,
+	input  reg_num   decode_rd,
+	input  ptr       decode_branch_offset,
+	input  alu_op    decode_data_op,
+	input  ptr       fetch_insn_pc,
+	input  psr_flags alu_flags,
+
+	output logic     stall,
+	                 branch,
+	                 writeback,
+	output reg_num   rd,
+	output ptr       branch_target,
+	                 pc,
+	                 pc_visible,
+	output psr_mode  reg_mode,
+	output alu_op    data_op,
+	output psr_flags flags,
+	                 next_flags
 );
 
 	enum
@@ -27,11 +34,13 @@ module core_cycles
 	assign stall = next_cycle != EXECUTE;
 	assign pc_visible = pc + 2;
 	assign next_cycle = EXECUTE; //TODO
+	assign next_flags = alu_flags; //TODO
 	assign reg_mode = `MODE_SVC; //TODO
 
 	always_ff @(posedge clk) begin
 		cycle <= next_cycle;
 		stall <= next_cycle != EXECUTE;
+		flags <= next_flags;
 
 		if(next_cycle == EXECUTE) begin
 			branch <= 0;
@@ -45,6 +54,8 @@ module core_cycles
 			end
 
 			pc <= fetch_insn_pc;
+			rd <= decode_rd;
+			data_op <= decode_data_op;
 		end
 	end
 
-- 
cgit v1.2.3