From f06c23ac1327850eeeb390e155bfc6330d302a77 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Fri, 29 Sep 2023 05:34:27 -0600
Subject: qsf: enable ModelSim-Altera

---
 conspiracion.qsf | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/conspiracion.qsf b/conspiracion.qsf
index 56cb0ff..c833c4b 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -314,4 +314,6 @@ set_global_assignment -name SIGNALTAP_FILE bus_test.stp
 
 
 
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
-- 
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