From ed0bd705f94f6aea568ec8405534984a37770f21 Mon Sep 17 00:00:00 2001
From: Alejandro Soto <alejandro@34project.org>
Date: Mon, 25 Sep 2023 19:12:49 -0600
Subject: rtl/core, tb: replace bus_master with a new top-level module

---
 conspiracion.qsf               |  67 +-----------
 conspiracion_bus_master_hw.tcl | 159 ----------------------------
 core_hw.tcl                    | 218 ++++++++++++++++++++++++++++++++++++++
 platform.qsys                  | 234 ++++++++++++++++-------------------------
 rtl/bus_master.sv              |  73 -------------
 rtl/core/control/mul.sv        |  67 ------------
 rtl/core/control/mul_fu.sv     |  67 ++++++++++++
 rtl/core/control/psr.sv        |  81 --------------
 rtl/core/control/status.sv     |  81 ++++++++++++++
 rtl/core/core.sv               |  91 ++++++++++++++++
 rtl/core/decode/branch.sv      |  18 ----
 rtl/core/decode/branch_dec.sv  |  18 ++++
 rtl/core/decode/coproc.sv      |  24 -----
 rtl/core/decode/coproc_dec.sv  |  24 +++++
 rtl/core/decode/data.sv        |  65 ------------
 rtl/core/decode/data_dec.sv    |  65 ++++++++++++
 rtl/core/decode/mul.sv         |  33 ------
 rtl/core/decode/mul_dec.sv     |  33 ++++++
 rtl/core/regs/map.sv           |  30 ------
 rtl/core/regs/reg_map.sv       |  30 ++++++
 rtl/top/conspiracion.sv        |  47 ++-------
 tb/platform.sv                 | 118 ++++++++++-----------
 tb/top/conspiracion.cpp        |  11 +-
 23 files changed, 791 insertions(+), 863 deletions(-)
 delete mode 100644 conspiracion_bus_master_hw.tcl
 create mode 100644 core_hw.tcl
 delete mode 100644 rtl/bus_master.sv
 delete mode 100644 rtl/core/control/mul.sv
 create mode 100644 rtl/core/control/mul_fu.sv
 delete mode 100644 rtl/core/control/psr.sv
 create mode 100644 rtl/core/control/status.sv
 create mode 100644 rtl/core/core.sv
 delete mode 100644 rtl/core/decode/branch.sv
 create mode 100644 rtl/core/decode/branch_dec.sv
 delete mode 100644 rtl/core/decode/coproc.sv
 create mode 100644 rtl/core/decode/coproc_dec.sv
 delete mode 100644 rtl/core/decode/data.sv
 create mode 100644 rtl/core/decode/data_dec.sv
 delete mode 100644 rtl/core/decode/mul.sv
 create mode 100644 rtl/core/decode/mul_dec.sv
 delete mode 100644 rtl/core/regs/map.sv
 create mode 100644 rtl/core/regs/reg_map.sv

diff --git a/conspiracion.qsf b/conspiracion.qsf
index 37342c3..56cb0ff 100644
--- a/conspiracion.qsf
+++ b/conspiracion.qsf
@@ -201,72 +201,6 @@ set_location_assignment PIN_AA13 -to vram_wire_we_n
 
 set_global_assignment -name SEARCH_PATH rtl
 
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/add.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/and.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/alu.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/orr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/alu/xor.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/arm810.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/branch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/control.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/coproc.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/cycles.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/data.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/debug.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/exception.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/issue.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/mul.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/ldst.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/pop.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/ldst/sizes.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/psr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/select.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/stall.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/control/writeback.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cache.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cache_lockdown.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cp15.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cpuid.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/cyclecnt.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/domain.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/far.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/fsr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/map.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/syscfg.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/tlb.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/tlb_lockdown.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/cp15/ttbr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/branch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/coproc.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/data.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/decode.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/isa.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/mrs.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/msr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/mul.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/mux.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/addr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/misc.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/multiple.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/ldst/single.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/decode/snd.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/fetch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/fetch/prefetch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/arbiter.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/fault.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/format.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/mmu.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mmu/pagewalk.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/mul.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/conds.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/porch/porch.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/psr.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/file.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/regs.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/regs/map.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/shifter.sv
-set_global_assignment -name SYSTEMVERILOG_FILE rtl/core/uarch.sv
-
 set_global_assignment -name QSYS_FILE platform.qsys
 set_global_assignment -name SYSTEMVERILOG_FILE rtl/top/conspiracion.sv
 set_global_assignment -name QIP_FILE platform/synthesis/platform.qip
@@ -379,4 +313,5 @@ set_global_assignment -name SIGNALTAP_FILE bus_test.stp
 
 
 
+
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/conspiracion_bus_master_hw.tcl b/conspiracion_bus_master_hw.tcl
deleted file mode 100644
index a83c642..0000000
--- a/conspiracion_bus_master_hw.tcl
+++ /dev/null
@@ -1,159 +0,0 @@
-# TCL File Generated by Component Editor 20.1
-# Wed Nov 16 05:30:25 GMT 2022
-# DO NOT MODIFY
-
-
-# 
-# conspiracion_bus_master "Toplevel bus master" v1.0
-#  2022.11.16.05:30:25
-# 
-# 
-
-# 
-# request TCL package from ACDS 16.1
-# 
-package require -exact qsys 16.1
-
-
-# 
-# module conspiracion_bus_master
-# 
-set_module_property DESCRIPTION ""
-set_module_property NAME conspiracion_bus_master
-set_module_property VERSION 1.0
-set_module_property INTERNAL false
-set_module_property OPAQUE_ADDRESS_MAP true
-set_module_property AUTHOR ""
-set_module_property DISPLAY_NAME "Toplevel bus master"
-set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
-set_module_property EDITABLE true
-set_module_property REPORT_TO_TALKBACK false
-set_module_property ALLOW_GREYBOX_GENERATION false
-set_module_property REPORT_HIERARCHY false
-
-
-# 
-# file sets
-# 
-add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
-set_fileset_property QUARTUS_SYNTH TOP_LEVEL bus_master
-set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
-set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
-add_fileset_file bus_master.sv SYSTEM_VERILOG PATH rtl/bus_master.sv
-
-
-# 
-# parameters
-# 
-
-
-# 
-# display items
-# 
-
-
-# 
-# connection point clock
-# 
-add_interface clock clock end
-set_interface_property clock clockRate 0
-set_interface_property clock ENABLED true
-set_interface_property clock EXPORT_OF ""
-set_interface_property clock PORT_NAME_MAP ""
-set_interface_property clock CMSIS_SVD_VARIABLES ""
-set_interface_property clock SVD_ADDRESS_GROUP ""
-
-add_interface_port clock clk clk Input 1
-
-
-# 
-# connection point reset_sink
-# 
-add_interface reset_sink reset end
-set_interface_property reset_sink associatedClock clock
-set_interface_property reset_sink synchronousEdges DEASSERT
-set_interface_property reset_sink ENABLED true
-set_interface_property reset_sink EXPORT_OF ""
-set_interface_property reset_sink PORT_NAME_MAP ""
-set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
-set_interface_property reset_sink SVD_ADDRESS_GROUP ""
-
-add_interface_port reset_sink rst_n reset_n Input 1
-
-
-# 
-# connection point core
-# 
-add_interface core conduit end
-set_interface_property core associatedClock clock
-set_interface_property core associatedReset reset_sink
-set_interface_property core ENABLED true
-set_interface_property core EXPORT_OF ""
-set_interface_property core PORT_NAME_MAP ""
-set_interface_property core CMSIS_SVD_VARIABLES ""
-set_interface_property core SVD_ADDRESS_GROUP ""
-
-add_interface_port core addr addr Input 30
-add_interface_port core data_rd data_rd Output 32
-add_interface_port core data_wr data_wr Input 32
-add_interface_port core ready ready Output 1
-add_interface_port core write write Input 1
-add_interface_port core start start Input 1
-add_interface_port core irq irq Output 1
-add_interface_port core cpu_clk cpu_clk Output 1
-add_interface_port core cpu_rst_n cpu_rst_n Output 1
-add_interface_port core data_be data_be Input 4
-
-
-# 
-# connection point irq
-# 
-add_interface irq interrupt start
-set_interface_property irq associatedAddressablePoint avalon_master_1_1
-set_interface_property irq associatedClock clock
-set_interface_property irq associatedReset reset_sink
-set_interface_property irq irqScheme INDIVIDUAL_REQUESTS
-set_interface_property irq ENABLED true
-set_interface_property irq EXPORT_OF ""
-set_interface_property irq PORT_NAME_MAP ""
-set_interface_property irq CMSIS_SVD_VARIABLES ""
-set_interface_property irq SVD_ADDRESS_GROUP ""
-
-add_interface_port irq avl_irq irq Input 1
-
-
-# 
-# connection point avalon_master_1_1
-# 
-add_interface avalon_master_1_1 avalon start
-set_interface_property avalon_master_1_1 addressUnits SYMBOLS
-set_interface_property avalon_master_1_1 associatedClock clock
-set_interface_property avalon_master_1_1 associatedReset reset_sink
-set_interface_property avalon_master_1_1 bitsPerSymbol 8
-set_interface_property avalon_master_1_1 burstOnBurstBoundariesOnly false
-set_interface_property avalon_master_1_1 burstcountUnits WORDS
-set_interface_property avalon_master_1_1 doStreamReads false
-set_interface_property avalon_master_1_1 doStreamWrites false
-set_interface_property avalon_master_1_1 holdTime 0
-set_interface_property avalon_master_1_1 linewrapBursts false
-set_interface_property avalon_master_1_1 maximumPendingReadTransactions 0
-set_interface_property avalon_master_1_1 maximumPendingWriteTransactions 0
-set_interface_property avalon_master_1_1 readLatency 0
-set_interface_property avalon_master_1_1 readWaitTime 1
-set_interface_property avalon_master_1_1 setupTime 0
-set_interface_property avalon_master_1_1 timingUnits Cycles
-set_interface_property avalon_master_1_1 writeWaitTime 0
-set_interface_property avalon_master_1_1 ENABLED true
-set_interface_property avalon_master_1_1 EXPORT_OF ""
-set_interface_property avalon_master_1_1 PORT_NAME_MAP ""
-set_interface_property avalon_master_1_1 CMSIS_SVD_VARIABLES ""
-set_interface_property avalon_master_1_1 SVD_ADDRESS_GROUP ""
-
-add_interface_port avalon_master_1_1 avl_address address Output 32
-add_interface_port avalon_master_1_1 avl_read read Output 1
-add_interface_port avalon_master_1_1 avl_readdata readdata Input 32
-add_interface_port avalon_master_1_1 avl_write write Output 1
-add_interface_port avalon_master_1_1 avl_writedata writedata Output 32
-add_interface_port avalon_master_1_1 avl_byteenable byteenable Output 4
-add_interface_port avalon_master_1_1 avl_waitrequest waitrequest Input 1
-
diff --git a/core_hw.tcl b/core_hw.tcl
new file mode 100644
index 0000000..852e6c5
--- /dev/null
+++ b/core_hw.tcl
@@ -0,0 +1,218 @@
+# TCL File Generated by Component Editor 20.1
+# Tue Sep 26 02:59:33 GMT 2023
+# DO NOT MODIFY
+
+
+# 
+# core "ARM810 CPU" v1.0
+#  2023.09.26.02:59:33
+# 
+# 
+
+# 
+# request TCL package from ACDS 16.1
+# 
+package require -exact qsys 16.1
+
+
+# 
+# module core
+# 
+set_module_property DESCRIPTION ""
+set_module_property NAME core
+set_module_property VERSION 1.0
+set_module_property INTERNAL false
+set_module_property OPAQUE_ADDRESS_MAP true
+set_module_property AUTHOR ""
+set_module_property DISPLAY_NAME "ARM810 CPU"
+set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
+set_module_property EDITABLE true
+set_module_property REPORT_TO_TALKBACK false
+set_module_property ALLOW_GREYBOX_GENERATION false
+set_module_property REPORT_HIERARCHY false
+
+
+# 
+# file sets
+# 
+add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
+set_fileset_property QUARTUS_SYNTH TOP_LEVEL core
+set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
+set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
+add_fileset_file core.sv SYSTEM_VERILOG PATH rtl/core/core.sv TOP_LEVEL_FILE
+add_fileset_file arm810.sv SYSTEM_VERILOG PATH rtl/core/arm810.sv
+add_fileset_file mul.sv SYSTEM_VERILOG PATH rtl/core/mul.sv
+add_fileset_file psr.sv SYSTEM_VERILOG PATH rtl/core/psr.sv
+add_fileset_file shifter.sv SYSTEM_VERILOG PATH rtl/core/shifter.sv
+add_fileset_file uarch.sv SYSTEM_VERILOG PATH rtl/core/uarch.sv
+add_fileset_file add.sv SYSTEM_VERILOG PATH rtl/core/alu/add.sv
+add_fileset_file alu.sv SYSTEM_VERILOG PATH rtl/core/alu/alu.sv
+add_fileset_file and.sv SYSTEM_VERILOG PATH rtl/core/alu/and.sv
+add_fileset_file orr.sv SYSTEM_VERILOG PATH rtl/core/alu/orr.sv
+add_fileset_file xor.sv SYSTEM_VERILOG PATH rtl/core/alu/xor.sv
+add_fileset_file branch.sv SYSTEM_VERILOG PATH rtl/core/control/branch.sv
+add_fileset_file control.sv SYSTEM_VERILOG PATH rtl/core/control/control.sv
+add_fileset_file coproc.sv SYSTEM_VERILOG PATH rtl/core/control/coproc.sv
+add_fileset_file cycles.sv SYSTEM_VERILOG PATH rtl/core/control/cycles.sv
+add_fileset_file data.sv SYSTEM_VERILOG PATH rtl/core/control/data.sv
+add_fileset_file debug.sv SYSTEM_VERILOG PATH rtl/core/control/debug.sv
+add_fileset_file exception.sv SYSTEM_VERILOG PATH rtl/core/control/exception.sv
+add_fileset_file issue.sv SYSTEM_VERILOG PATH rtl/core/control/issue.sv
+add_fileset_file mul_fu.sv SYSTEM_VERILOG PATH rtl/core/control/mul_fu.sv
+add_fileset_file select.sv SYSTEM_VERILOG PATH rtl/core/control/select.sv
+add_fileset_file stall.sv SYSTEM_VERILOG PATH rtl/core/control/stall.sv
+add_fileset_file status.sv SYSTEM_VERILOG PATH rtl/core/control/status.sv
+add_fileset_file writeback.sv SYSTEM_VERILOG PATH rtl/core/control/writeback.sv
+add_fileset_file ldst.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/ldst.sv
+add_fileset_file pop.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/pop.sv
+add_fileset_file sizes.sv SYSTEM_VERILOG PATH rtl/core/control/ldst/sizes.sv
+add_fileset_file cache.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache.sv
+add_fileset_file cache_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/cache_lockdown.sv
+add_fileset_file cp15.sv SYSTEM_VERILOG PATH rtl/core/cp15/cp15.sv
+add_fileset_file cpuid.sv SYSTEM_VERILOG PATH rtl/core/cp15/cpuid.sv
+add_fileset_file cyclecnt.sv SYSTEM_VERILOG PATH rtl/core/cp15/cyclecnt.sv
+add_fileset_file domain.sv SYSTEM_VERILOG PATH rtl/core/cp15/domain.sv
+add_fileset_file far.sv SYSTEM_VERILOG PATH rtl/core/cp15/far.sv
+add_fileset_file fsr.sv SYSTEM_VERILOG PATH rtl/core/cp15/fsr.sv
+add_fileset_file map.sv SYSTEM_VERILOG PATH rtl/core/cp15/map.sv
+add_fileset_file syscfg.sv SYSTEM_VERILOG PATH rtl/core/cp15/syscfg.sv
+add_fileset_file tlb.sv SYSTEM_VERILOG PATH rtl/core/cp15/tlb.sv
+add_fileset_file tlb_lockdown.sv SYSTEM_VERILOG PATH rtl/core/cp15/tlb_lockdown.sv
+add_fileset_file ttbr.sv SYSTEM_VERILOG PATH rtl/core/cp15/ttbr.sv
+add_fileset_file branch_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/branch_dec.sv
+add_fileset_file coproc_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/coproc_dec.sv
+add_fileset_file data_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/data_dec.sv
+add_fileset_file decode.sv SYSTEM_VERILOG PATH rtl/core/decode/decode.sv
+add_fileset_file isa.sv SYSTEM_VERILOG PATH rtl/core/decode/isa.sv
+add_fileset_file mrs.sv SYSTEM_VERILOG PATH rtl/core/decode/mrs.sv
+add_fileset_file msr.sv SYSTEM_VERILOG PATH rtl/core/decode/msr.sv
+add_fileset_file mul_dec.sv SYSTEM_VERILOG PATH rtl/core/decode/mul_dec.sv
+add_fileset_file mux.sv SYSTEM_VERILOG PATH rtl/core/decode/mux.sv
+add_fileset_file snd.sv SYSTEM_VERILOG PATH rtl/core/decode/snd.sv
+add_fileset_file addr.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/addr.sv
+add_fileset_file misc.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/misc.sv
+add_fileset_file multiple.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/multiple.sv
+add_fileset_file single.sv SYSTEM_VERILOG PATH rtl/core/decode/ldst/single.sv
+add_fileset_file fetch.sv SYSTEM_VERILOG PATH rtl/core/fetch/fetch.sv
+add_fileset_file prefetch.sv SYSTEM_VERILOG PATH rtl/core/fetch/prefetch.sv
+add_fileset_file arbiter.sv SYSTEM_VERILOG PATH rtl/core/mmu/arbiter.sv
+add_fileset_file fault.sv SYSTEM_VERILOG PATH rtl/core/mmu/fault.sv
+add_fileset_file format.sv SYSTEM_VERILOG PATH rtl/core/mmu/format.sv
+add_fileset_file mmu.sv SYSTEM_VERILOG PATH rtl/core/mmu/mmu.sv
+add_fileset_file pagewalk.sv SYSTEM_VERILOG PATH rtl/core/mmu/pagewalk.sv
+add_fileset_file conds.sv SYSTEM_VERILOG PATH rtl/core/porch/conds.sv
+add_fileset_file porch.sv SYSTEM_VERILOG PATH rtl/core/porch/porch.sv
+add_fileset_file file.sv SYSTEM_VERILOG PATH rtl/core/regs/file.sv
+add_fileset_file reg_map.sv SYSTEM_VERILOG PATH rtl/core/regs/reg_map.sv
+add_fileset_file regs.sv SYSTEM_VERILOG PATH rtl/core/regs/regs.sv
+
+
+# 
+# parameters
+# 
+
+
+# 
+# display items
+# 
+
+
+# 
+# connection point clock_sink
+# 
+add_interface clock_sink clock end
+set_interface_property clock_sink clockRate 0
+set_interface_property clock_sink ENABLED true
+set_interface_property clock_sink EXPORT_OF ""
+set_interface_property clock_sink PORT_NAME_MAP ""
+set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
+set_interface_property clock_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port clock_sink clk clk Input 1
+
+
+# 
+# connection point master
+# 
+add_interface master avalon start
+set_interface_property master addressUnits SYMBOLS
+set_interface_property master associatedClock clock_sink
+set_interface_property master associatedReset reset_sink
+set_interface_property master bitsPerSymbol 8
+set_interface_property master burstOnBurstBoundariesOnly false
+set_interface_property master burstcountUnits WORDS
+set_interface_property master doStreamReads false
+set_interface_property master doStreamWrites false
+set_interface_property master holdTime 0
+set_interface_property master linewrapBursts false
+set_interface_property master maximumPendingReadTransactions 0
+set_interface_property master maximumPendingWriteTransactions 0
+set_interface_property master readLatency 0
+set_interface_property master readWaitTime 1
+set_interface_property master setupTime 0
+set_interface_property master timingUnits Cycles
+set_interface_property master writeWaitTime 0
+set_interface_property master ENABLED true
+set_interface_property master EXPORT_OF ""
+set_interface_property master PORT_NAME_MAP ""
+set_interface_property master CMSIS_SVD_VARIABLES ""
+set_interface_property master SVD_ADDRESS_GROUP ""
+
+add_interface_port master avl_address address Output 32
+add_interface_port master avl_read read Output 1
+add_interface_port master avl_write write Output 1
+add_interface_port master avl_readdata readdata Input 32
+add_interface_port master avl_writedata writedata Output 32
+add_interface_port master avl_waitrequest waitrequest Input 1
+add_interface_port master avl_byteenable byteenable Output 4
+
+
+# 
+# connection point interrupt_receiver
+# 
+add_interface interrupt_receiver interrupt start
+set_interface_property interrupt_receiver associatedAddressablePoint ""
+set_interface_property interrupt_receiver associatedClock clock_sink
+set_interface_property interrupt_receiver associatedReset reset_sink
+set_interface_property interrupt_receiver irqScheme INDIVIDUAL_REQUESTS
+set_interface_property interrupt_receiver ENABLED true
+set_interface_property interrupt_receiver EXPORT_OF ""
+set_interface_property interrupt_receiver PORT_NAME_MAP ""
+set_interface_property interrupt_receiver CMSIS_SVD_VARIABLES ""
+set_interface_property interrupt_receiver SVD_ADDRESS_GROUP ""
+
+add_interface_port interrupt_receiver avl_irq irq Input 1
+
+
+# 
+# connection point reset_sink
+# 
+add_interface reset_sink reset end
+set_interface_property reset_sink associatedClock clock_sink
+set_interface_property reset_sink synchronousEdges DEASSERT
+set_interface_property reset_sink ENABLED true
+set_interface_property reset_sink EXPORT_OF ""
+set_interface_property reset_sink PORT_NAME_MAP ""
+set_interface_property reset_sink CMSIS_SVD_VARIABLES ""
+set_interface_property reset_sink SVD_ADDRESS_GROUP ""
+
+add_interface_port reset_sink rst_n reset_n Input 1
+
+
+# 
+# connection point mp
+# 
+add_interface mp conduit end
+set_interface_property mp associatedClock clock_sink
+set_interface_property mp associatedReset reset_sink
+set_interface_property mp ENABLED true
+set_interface_property mp EXPORT_OF ""
+set_interface_property mp PORT_NAME_MAP ""
+set_interface_property mp CMSIS_SVD_VARIABLES ""
+set_interface_property mp SVD_ADDRESS_GROUP ""
+
+add_interface_port mp step step Input 1
+add_interface_port mp cpu_halt cpu_halt Input 1
+add_interface_port mp cpu_halted cpu_halted Output 1
+add_interface_port mp breakpoint breakpoint Output 1
+
diff --git a/platform.qsys b/platform.qsys
index 5dd6c0d..67399ba 100644
--- a/platform.qsys
+++ b/platform.qsys
@@ -13,7 +13,7 @@
    {
       datum _sortIndex
       {
-         value = "3";
+         value = "2";
          type = "int";
       }
    }
@@ -21,7 +21,7 @@
    {
       datum _sortIndex
       {
-         value = "17";
+         value = "16";
          type = "int";
       }
    }
@@ -29,7 +29,15 @@
    {
       datum _sortIndex
       {
-         value = "1";
+         value = "0";
+         type = "int";
+      }
+   }
+   element cpu_0
+   {
+      datum _sortIndex
+      {
+         value = "19";
          type = "int";
       }
    }
@@ -37,7 +45,7 @@
    {
       datum _sortIndex
       {
-         value = "2";
+         value = "1";
          type = "int";
       }
    }
@@ -45,7 +53,7 @@
    {
       datum _sortIndex
       {
-         value = "18";
+         value = "17";
          type = "int";
       }
    }
@@ -53,7 +61,7 @@
    {
       datum _sortIndex
       {
-         value = "9";
+         value = "8";
          type = "int";
       }
    }
@@ -61,15 +69,15 @@
    {
       datum _sortIndex
       {
-         value = "6";
+         value = "5";
          type = "int";
       }
    }
-   element master_0
+   element mm_bridge_1
    {
       datum _sortIndex
       {
-         value = "0";
+         value = "18";
          type = "int";
       }
    }
@@ -77,7 +85,7 @@
    {
       datum _sortIndex
       {
-         value = "8";
+         value = "7";
          type = "int";
       }
    }
@@ -85,7 +93,7 @@
    {
       datum _sortIndex
       {
-         value = "13";
+         value = "12";
          type = "int";
       }
    }
@@ -93,7 +101,7 @@
    {
       datum _sortIndex
       {
-         value = "15";
+         value = "14";
          type = "int";
       }
    }
@@ -101,12 +109,12 @@
    {
       datum _sortIndex
       {
-         value = "14";
+         value = "13";
          type = "int";
       }
       datum sopceditor_expanded
       {
-         value = "0";
+         value = "1";
          type = "boolean";
       }
    }
@@ -146,7 +154,7 @@
    {
       datum _sortIndex
       {
-         value = "4";
+         value = "3";
          type = "int";
       }
    }
@@ -154,7 +162,7 @@
    {
       datum _sortIndex
       {
-         value = "16";
+         value = "15";
          type = "int";
       }
    }
@@ -162,7 +170,7 @@
    {
       datum _sortIndex
       {
-         value = "10";
+         value = "9";
          type = "int";
       }
    }
@@ -170,7 +178,7 @@
    {
       datum _sortIndex
       {
-         value = "7";
+         value = "6";
          type = "int";
       }
    }
@@ -178,7 +186,7 @@
    {
       datum _sortIndex
       {
-         value = "12";
+         value = "11";
          type = "int";
       }
       datum sopceditor_expanded
@@ -191,7 +199,7 @@
    {
       datum _sortIndex
       {
-         value = "11";
+         value = "10";
          type = "int";
       }
    }
@@ -199,7 +207,7 @@
    {
       datum _sortIndex
       {
-         value = "5";
+         value = "4";
          type = "int";
       }
    }
@@ -230,12 +238,8 @@
    type="conduit"
    dir="end" />
  <interface name="clk" internal="clk_0.clk_in" type="clock" dir="end" />
- <interface name="master_0_conduit_end" internal="master_0.conduit_end" />
- <interface
-   name="master_0_core"
-   internal="master_0.core"
-   type="conduit"
-   dir="end" />
+ <interface name="cpu_0_mp" internal="cpu_0.mp" type="conduit" dir="end" />
+ <interface name="cpu_0_mp_1" internal="cpu_0.mp_1" />
  <interface name="memory" internal="hps_0.memory" type="conduit" dir="end" />
  <interface
    name="pio_0_external_connection"
@@ -295,6 +299,9 @@
   <parameter name="inputClockFrequency" value="0" />
   <parameter name="resetSynchronousEdges" value="NONE" />
  </module>
+ <module name="cpu_0" kind="core" version="1.0" enabled="1">
+  <parameter name="AUTO_INTERRUPT_RECEIVER_INTERRUPTS_USED" value="1" />
+ </module>
  <module name="hps_0" kind="altera_hps" version="20.1" enabled="1">
   <parameter name="ABSTRACT_REAL_COMPARE_TEST" value="false" />
   <parameter name="ABS_RAM_MEM_INIT_FILENAME" value="meminit" />
@@ -863,11 +870,22 @@
   <parameter name="writeIRQThreshold" value="8" />
  </module>
  <module
-   name="master_0"
-   kind="conspiracion_bus_master"
-   version="1.0"
+   name="mm_bridge_1"
+   kind="altera_avalon_mm_bridge"
+   version="20.1"
    enabled="1">
-  <parameter name="AUTO_IRQ_INTERRUPTS_USED" value="1" />
+  <parameter name="ADDRESS_UNITS" value="SYMBOLS" />
+  <parameter name="ADDRESS_WIDTH" value="32" />
+  <parameter name="DATA_WIDTH" value="32" />
+  <parameter name="LINEWRAPBURSTS" value="0" />
+  <parameter name="MAX_BURST_SIZE" value="1" />
+  <parameter name="MAX_PENDING_RESPONSES" value="4" />
+  <parameter name="PIPELINE_COMMAND" value="1" />
+  <parameter name="PIPELINE_RESPONSE" value="1" />
+  <parameter name="SYMBOL_WIDTH" value="8" />
+  <parameter name="SYSINFO_ADDR_WIDTH" value="30" />
+  <parameter name="USE_AUTO_ADDRESS_WIDTH" value="0" />
+  <parameter name="USE_RESPONSE" value="0" />
  </module>
  <module name="pio_0" kind="altera_avalon_pio" version="20.1" enabled="1">
   <parameter name="bitClearingEdgeCapReg" value="false" />
@@ -1221,96 +1239,6 @@
   <parameter name="registerDataIn" value="true" />
   <parameter name="rowWidth" value="13" />
  </module>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="pixdma.avalon_control_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30030000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="jtag_uart_0.avalon_jtag_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="pixfmt.avalon_rgb_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30040000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="intc_0.avalon_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30070000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="pio_0.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30010000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="timer_0.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30020000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="vram.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x38000000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="switches.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30060000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="buttons.s1">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30050000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
- <connection
-   kind="avalon"
-   version="20.1"
-   start="master_0.avalon_master_1_1"
-   end="address_span_extender_0.windowed_slave">
-  <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x0000" />
-  <parameter name="defaultConnection" value="false" />
- </connection>
  <connection
    kind="avalon"
    version="20.1"
@@ -1332,7 +1260,7 @@
  <connection
    kind="avalon"
    version="20.1"
-   start="jtag_dbg.master"
+   start="mm_bridge_1.m0"
    end="pixdma.avalon_control_slave">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30030000" />
@@ -1341,7 +1269,7 @@
  <connection
    kind="avalon"
    version="20.1"
-   start="jtag_dbg.master"
+   start="mm_bridge_1.m0"
    end="jtag_uart_0.avalon_jtag_slave">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30000000" />
@@ -1350,7 +1278,7 @@
  <connection
    kind="avalon"
    version="20.1"
-   start="jtag_dbg.master"
+   start="mm_bridge_1.m0"
    end="pixfmt.avalon_rgb_slave">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30040000" />
@@ -1359,23 +1287,33 @@
  <connection
    kind="avalon"
    version="20.1"
-   start="jtag_dbg.master"
+   start="mm_bridge_1.m0"
    end="intc_0.avalon_slave">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30070000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection kind="avalon" version="20.1" start="jtag_dbg.master" end="pio_0.s1">
+ <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="buttons.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x30050000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="pio_0.s1">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30010000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection kind="avalon" version="20.1" start="jtag_dbg.master" end="timer_0.s1">
+ <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="switches.s1">
+  <parameter name="arbitrationPriority" value="1" />
+  <parameter name="baseAddress" value="0x30060000" />
+  <parameter name="defaultConnection" value="false" />
+ </connection>
+ <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="timer_0.s1">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x30020000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection kind="avalon" version="20.1" start="jtag_dbg.master" end="vram.s1">
+ <connection kind="avalon" version="20.1" start="mm_bridge_1.m0" end="vram.s1">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x38000000" />
   <parameter name="defaultConnection" value="false" />
@@ -1383,22 +1321,26 @@
  <connection
    kind="avalon"
    version="20.1"
-   start="jtag_dbg.master"
-   end="switches.s1">
+   start="mm_bridge_1.m0"
+   end="address_span_extender_0.windowed_slave">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30060000" />
+  <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
- <connection kind="avalon" version="20.1" start="jtag_dbg.master" end="buttons.s1">
+ <connection
+   kind="avalon"
+   version="20.1"
+   start="jtag_dbg.master"
+   end="mm_bridge_1.s0">
   <parameter name="arbitrationPriority" value="1" />
-  <parameter name="baseAddress" value="0x30050000" />
+  <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
  </connection>
  <connection
    kind="avalon"
    version="20.1"
-   start="jtag_dbg.master"
-   end="address_span_extender_0.windowed_slave">
+   start="cpu_0.master"
+   end="mm_bridge_1.s0">
   <parameter name="arbitrationPriority" value="1" />
   <parameter name="baseAddress" value="0x0000" />
   <parameter name="defaultConnection" value="false" />
@@ -1458,7 +1400,12 @@
    kind="clock"
    version="20.1"
    start="pll_0.outclk1"
-   end="master_0.clock" />
+   end="mm_bridge_1.clk" />
+ <connection
+   kind="clock"
+   version="20.1"
+   start="pll_0.outclk1"
+   end="cpu_0.clock_sink" />
  <connection
    kind="clock"
    version="20.1"
@@ -1495,15 +1442,15 @@
  <connection
    kind="interrupt"
    version="20.1"
-   start="intc_0.interrupt_timer"
-   end="timer_0.irq">
+   start="cpu_0.interrupt_receiver"
+   end="intc_0.interrupt_sender">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
    kind="interrupt"
    version="20.1"
-   start="master_0.irq"
-   end="intc_0.interrupt_sender">
+   start="intc_0.interrupt_timer"
+   end="timer_0.irq">
   <parameter name="irqNumber" value="0" />
  </connection>
  <connection
@@ -1551,12 +1498,17 @@
    kind="reset"
    version="20.1"
    start="clk_0.clk_reset"
-   end="master_0.reset_sink" />
+   end="mm_bridge_1.reset" />
  <connection
    kind="reset"
    version="20.1"
    start="clk_0.clk_reset"
    end="intc_0.reset_sink" />
+ <connection
+   kind="reset"
+   version="20.1"
+   start="clk_0.clk_reset"
+   end="cpu_0.reset_sink" />
  <connection
    kind="reset"
    version="20.1"
diff --git a/rtl/bus_master.sv b/rtl/bus_master.sv
deleted file mode 100644
index 0c6af55..0000000
--- a/rtl/bus_master.sv
+++ /dev/null
@@ -1,73 +0,0 @@
-module bus_master
-(
-	input  logic       clk,
-	                   rst_n,
-
-	input  logic[29:0] addr,
-	input  logic       start,
-	                   write,
-	output logic       ready,
-	output logic[31:0] data_rd,
-	input  logic[31:0] data_wr,
-	input  logic[3:0]  data_be,
-	output logic       cpu_clk,
-	                   cpu_rst_n,
-	                   irq,
-
-	output logic[31:0] avl_address,
-	output logic       avl_read,
-	                   avl_write,
-	input  logic[31:0] avl_readdata,
-	output logic[31:0] avl_writedata,
-	input  logic       avl_waitrequest,
-	output logic[3:0]  avl_byteenable,
-	input  logic       avl_irq
-);
-
-	enum int unsigned
-	{
-		IDLE,
-		WAIT
-	} state;
-
-	assign irq = avl_irq;
-	assign cpu_clk = clk;
-	assign cpu_rst_n = rst_n;
-
-	assign data_rd = avl_readdata;
-
-	always_comb
-		unique case(state)
-			IDLE: ready = 0;
-			WAIT: ready = !avl_waitrequest;
-		endcase
-
-	always_ff @(posedge clk or negedge rst_n)
-		/* P. 16:
-		 * A host must make no assumption about the assertion state of
-		 * waitrequest when the host is idle: waitrequest may be high or
-		 * low, depending on system properties. When waitrequest is asserted,
-		 * host control signals to the agent must remain constant except for
-		 * beginbursttransfer.
-		 */
-		if(!rst_n) begin
-			state <= IDLE;
-			avl_read <= 0;
-			avl_write <= 0;
-			avl_address <= 0;
-			avl_writedata <= 0;
-			avl_byteenable <= 0;
-		end else if((state == IDLE || !avl_waitrequest) && start) begin
-			state <= WAIT;
-			avl_read <= ~write;
-			avl_write <= write;
-			avl_address <= {addr, 2'b00};
-			avl_writedata <= data_wr;
-			avl_byteenable <= write ? data_be : 4'b1111;
-		end else if(state == WAIT && !avl_waitrequest) begin
-			state <= IDLE;
-			avl_read <= 0;
-			avl_write <= 0;
-		end
-
-endmodule
diff --git a/rtl/core/control/mul.sv b/rtl/core/control/mul.sv
deleted file mode 100644
index 8352435..0000000
--- a/rtl/core/control/mul.sv
+++ /dev/null
@@ -1,67 +0,0 @@
-`include "core/uarch.sv"
-
-module core_control_mul
-(
-	input  logic       clk,
-	                   rst_n,
-
-	input  insn_decode dec,
-	input  logic       mul_ready,
-	input  word        rd_value_a,
-	                   rd_value_b,
-
-	input  ctrl_cycle  cycle,
-	                   next_cycle,
-	input  logic       issue,
-
-	output word        mul_a,
-	                   mul_b,
-	                   mul_c_hi,
-	                   mul_c_lo,
-	output reg_num     mul_r_add_hi,
-	                   mul_r_add_lo,
-	output logic       mul,
-	                   mul_add,
-	                   mul_long,
-	                   mul_start,
-	                   mul_signed
-);
-
-	word hold_a, hold_b;
-
-	assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b};
-	assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b};
-
-	always_ff @(posedge clk or negedge rst_n)
-		if(!rst_n) begin
-			mul <= 0;
-			mul_add <= 0;
-			mul_long <= 0;
-			mul_start <= 0;
-			mul_signed <= 0;
-			mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}};
-			mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}};
-
-			hold_a <= 0;
-			hold_b <= 0;
-		end else begin
-			mul_start <= 0;
-
-			if(next_cycle.issue) begin
-				mul <= issue && dec.ctrl.mul;
-				mul_add <= dec.mul.add;
-				mul_long <= dec.mul.long_mul;
-				mul_signed <= dec.mul.signed_mul;
-				mul_r_add_hi <= dec.mul.r_add_hi;
-				mul_r_add_lo <= dec.mul.r_add_lo;
-			end else if(next_cycle.mul)
-				mul_start <= !cycle.mul;
-			else if(next_cycle.mul_acc_ld) begin
-				hold_a <= rd_value_a;
-				hold_b <= rd_value_b;
-			end
-		end
-
-	//TODO: mul update_flags
-
-endmodule
diff --git a/rtl/core/control/mul_fu.sv b/rtl/core/control/mul_fu.sv
new file mode 100644
index 0000000..8352435
--- /dev/null
+++ b/rtl/core/control/mul_fu.sv
@@ -0,0 +1,67 @@
+`include "core/uarch.sv"
+
+module core_control_mul
+(
+	input  logic       clk,
+	                   rst_n,
+
+	input  insn_decode dec,
+	input  logic       mul_ready,
+	input  word        rd_value_a,
+	                   rd_value_b,
+
+	input  ctrl_cycle  cycle,
+	                   next_cycle,
+	input  logic       issue,
+
+	output word        mul_a,
+	                   mul_b,
+	                   mul_c_hi,
+	                   mul_c_lo,
+	output reg_num     mul_r_add_hi,
+	                   mul_r_add_lo,
+	output logic       mul,
+	                   mul_add,
+	                   mul_long,
+	                   mul_start,
+	                   mul_signed
+);
+
+	word hold_a, hold_b;
+
+	assign {mul_c_hi, mul_c_lo} = {rd_value_a, rd_value_b};
+	assign {mul_a, mul_b} = mul_add ? {hold_a, hold_b} : {rd_value_a, rd_value_b};
+
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			mul <= 0;
+			mul_add <= 0;
+			mul_long <= 0;
+			mul_start <= 0;
+			mul_signed <= 0;
+			mul_r_add_hi <= {$bits(mul_r_add_hi){1'b0}};
+			mul_r_add_lo <= {$bits(mul_r_add_lo){1'b0}};
+
+			hold_a <= 0;
+			hold_b <= 0;
+		end else begin
+			mul_start <= 0;
+
+			if(next_cycle.issue) begin
+				mul <= issue && dec.ctrl.mul;
+				mul_add <= dec.mul.add;
+				mul_long <= dec.mul.long_mul;
+				mul_signed <= dec.mul.signed_mul;
+				mul_r_add_hi <= dec.mul.r_add_hi;
+				mul_r_add_lo <= dec.mul.r_add_lo;
+			end else if(next_cycle.mul)
+				mul_start <= !cycle.mul;
+			else if(next_cycle.mul_acc_ld) begin
+				hold_a <= rd_value_a;
+				hold_b <= rd_value_b;
+			end
+		end
+
+	//TODO: mul update_flags
+
+endmodule
diff --git a/rtl/core/control/psr.sv b/rtl/core/control/psr.sv
deleted file mode 100644
index 6616bc9..0000000
--- a/rtl/core/control/psr.sv
+++ /dev/null
@@ -1,81 +0,0 @@
-`include "core/uarch.sv"
-
-module core_control_psr
-(
-	input  logic       clk,
-	                   rst_n,
-
-	input  insn_decode dec,
-	input  word        cpsr_rd,
-	                   spsr_rd,
-	                   alu_b,
-	input  psr_mode    exception_mode,
-
-	input  ctrl_cycle  cycle,
-	                   next_cycle,
-	input  logic       issue,
-
-	output logic       psr,
-	                   psr_saved,
-	                   psr_write,
-	                   psr_wr_flags,
-	                   psr_wr_control,
-	                   final_psr_write,
-	                   final_restore_spsr,
-	output word        psr_wb,
-	                   psr_wr
-);
-
-	word exception_spsr;
-
-	assign psr_wb = psr_saved ? spsr_rd : cpsr_rd;
-
-	always_comb begin
-		psr_write = 0;
-
-		if(next_cycle.issue)
-			psr_write = final_psr_write || final_restore_spsr;
-
-		if(cycle.escalate || cycle.exception)
-			psr_write = 1;
-
-		if(cycle.escalate)
-			//TODO: F (FIQ) no cambia siempre
-			psr_wr = {24'b0, 3'b110, exception_mode};
-		else if(cycle.exception)
-			psr_wr = exception_spsr;
-		else
-			psr_wr = final_restore_spsr ? spsr_rd : alu_b;
-	end
-
-	always_ff @(posedge clk or negedge rst_n)
-		if(!rst_n) begin
-			psr <= 0;
-			psr_saved <= 0;
-			psr_wr_flags <= 0;
-			psr_wr_control <= 0;
-
-			exception_spsr <= 0;
-			final_psr_write <= 0;
-			final_restore_spsr <= 0;
-		end else if(next_cycle.issue) begin
-			psr <= issue && dec.ctrl.psr;
-			psr_saved <= dec.psr.saved;
-			psr_wr_flags <= dec.psr.wr_flags;
-			psr_wr_control <= dec.psr.wr_control;
-
-			final_psr_write <= issue && dec.psr.write;
-			final_restore_spsr <= issue && dec.psr.restore_spsr;
-		end else if(next_cycle.escalate) begin
-			psr_saved <= 0;
-			psr_wr_flags <= 0;
-			psr_wr_control <= 1;
-			exception_spsr <= cpsr_rd;
-		end else if(next_cycle.exception) begin
-			psr <= 0;
-			psr_saved <= 1;
-			psr_wr_flags <= 1;
-		end else if(next_cycle.psr)
-			psr <= 0;
-
-endmodule
diff --git a/rtl/core/control/status.sv b/rtl/core/control/status.sv
new file mode 100644
index 0000000..6616bc9
--- /dev/null
+++ b/rtl/core/control/status.sv
@@ -0,0 +1,81 @@
+`include "core/uarch.sv"
+
+module core_control_psr
+(
+	input  logic       clk,
+	                   rst_n,
+
+	input  insn_decode dec,
+	input  word        cpsr_rd,
+	                   spsr_rd,
+	                   alu_b,
+	input  psr_mode    exception_mode,
+
+	input  ctrl_cycle  cycle,
+	                   next_cycle,
+	input  logic       issue,
+
+	output logic       psr,
+	                   psr_saved,
+	                   psr_write,
+	                   psr_wr_flags,
+	                   psr_wr_control,
+	                   final_psr_write,
+	                   final_restore_spsr,
+	output word        psr_wb,
+	                   psr_wr
+);
+
+	word exception_spsr;
+
+	assign psr_wb = psr_saved ? spsr_rd : cpsr_rd;
+
+	always_comb begin
+		psr_write = 0;
+
+		if(next_cycle.issue)
+			psr_write = final_psr_write || final_restore_spsr;
+
+		if(cycle.escalate || cycle.exception)
+			psr_write = 1;
+
+		if(cycle.escalate)
+			//TODO: F (FIQ) no cambia siempre
+			psr_wr = {24'b0, 3'b110, exception_mode};
+		else if(cycle.exception)
+			psr_wr = exception_spsr;
+		else
+			psr_wr = final_restore_spsr ? spsr_rd : alu_b;
+	end
+
+	always_ff @(posedge clk or negedge rst_n)
+		if(!rst_n) begin
+			psr <= 0;
+			psr_saved <= 0;
+			psr_wr_flags <= 0;
+			psr_wr_control <= 0;
+
+			exception_spsr <= 0;
+			final_psr_write <= 0;
+			final_restore_spsr <= 0;
+		end else if(next_cycle.issue) begin
+			psr <= issue && dec.ctrl.psr;
+			psr_saved <= dec.psr.saved;
+			psr_wr_flags <= dec.psr.wr_flags;
+			psr_wr_control <= dec.psr.wr_control;
+
+			final_psr_write <= issue && dec.psr.write;
+			final_restore_spsr <= issue && dec.psr.restore_spsr;
+		end else if(next_cycle.escalate) begin
+			psr_saved <= 0;
+			psr_wr_flags <= 0;
+			psr_wr_control <= 1;
+			exception_spsr <= cpsr_rd;
+		end else if(next_cycle.exception) begin
+			psr <= 0;
+			psr_saved <= 1;
+			psr_wr_flags <= 1;
+		end else if(next_cycle.psr)
+			psr <= 0;
+
+endmodule
diff --git a/rtl/core/core.sv b/rtl/core/core.sv
new file mode 100644
index 0000000..8d487fa
--- /dev/null
+++ b/rtl/core/core.sv
@@ -0,0 +1,91 @@
+`include "core/uarch.sv"
+
+module core
+(
+	input  logic      clk,
+	                  rst_n,
+
+	input  wire       step,
+	input  wire       cpu_halt,
+	output wire       cpu_halted,
+	output wire       breakpoint,
+
+	output word       avl_address,
+	output logic      avl_read,
+	                  avl_write,
+	input  word       avl_readdata,
+	output word       avl_writedata,
+	input  logic      avl_waitrequest,
+	output logic[3:0] avl_byteenable,
+
+	input  logic      avl_irq
+);
+
+	logic ready, write, start;
+
+	logic[3:0] data_be;
+	logic[29:0] addr;
+	logic[31:0] data_rd, data_wr;
+
+	enum int unsigned
+	{
+		IDLE,
+		WAIT
+	} state;
+
+	arm810 cpu
+	(
+		.irq(avl_irq),
+		.halt(cpu_halt),
+		.halted(cpu_halted),
+		.bus_addr(addr),
+		.bus_data_rd(data_rd),
+		.bus_data_wr(data_wr),
+		.bus_data_be(data_be),
+		.bus_ready(ready),
+		.bus_write(write),
+		.bus_start(start),
+`ifndef VERILATOR
+		.step(0),
+		.breakpoint(),
+`endif
+		.*
+	);
+
+	assign data_rd = avl_readdata;
+
+	always_comb
+		unique case(state)
+			IDLE: ready = 0;
+			WAIT: ready = !avl_waitrequest;
+		endcase
+
+	always_ff @(posedge clk or negedge rst_n)
+		/* P. 16:
+		 * A host must make no assumption about the assertion state of
+		 * waitrequest when the host is idle: waitrequest may be high or
+		 * low, depending on system properties. When waitrequest is asserted,
+		 * host control signals to the agent must remain constant except for
+		 * beginbursttransfer.
+		 */
+		if(!rst_n) begin
+			state <= IDLE;
+			avl_read <= 0;
+			avl_write <= 0;
+			avl_address <= 0;
+			avl_writedata <= 0;
+			avl_byteenable <= 0;
+		end else if((state == IDLE || !avl_waitrequest) && start) begin
+			state <= WAIT;
+			avl_read <= ~write;
+			avl_write <= write;
+			avl_address <= {addr, 2'b00};
+			avl_writedata <= data_wr;
+			avl_byteenable <= write ? data_be : 4'b1111;
+		end else if(state == WAIT && !avl_waitrequest) begin
+			state <= IDLE;
+			avl_read <= 0;
+			avl_write <= 0;
+		end
+
+endmodule
diff --git a/rtl/core/decode/branch.sv b/rtl/core/decode/branch.sv
deleted file mode 100644
index 1dbc1ad..0000000
--- a/rtl/core/decode/branch.sv
+++ /dev/null
@@ -1,18 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_branch
-(
-	input  word  insn,
-
-	output logic link,
-	output ptr   offset
-);
-
-	logic[23:0] immediate;
-	assign immediate = insn `FIELD_B_OFFSET;
-
-	assign link = insn `FIELD_B_L;
-	assign offset = {{6{immediate[23]}}, immediate};
-
-endmodule
diff --git a/rtl/core/decode/branch_dec.sv b/rtl/core/decode/branch_dec.sv
new file mode 100644
index 0000000..1dbc1ad
--- /dev/null
+++ b/rtl/core/decode/branch_dec.sv
@@ -0,0 +1,18 @@
+`include "core/decode/isa.sv"
+`include "core/uarch.sv"
+
+module core_decode_branch
+(
+	input  word  insn,
+
+	output logic link,
+	output ptr   offset
+);
+
+	logic[23:0] immediate;
+	assign immediate = insn `FIELD_B_OFFSET;
+
+	assign link = insn `FIELD_B_L;
+	assign offset = {{6{immediate[23]}}, immediate};
+
+endmodule
diff --git a/rtl/core/decode/coproc.sv b/rtl/core/decode/coproc.sv
deleted file mode 100644
index 153cadf..0000000
--- a/rtl/core/decode/coproc.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_coproc
-(
-	input  word          insn,
-
-	output coproc_decode decode,
-	output reg_num       rd,
-	output logic         writeback,
-	                     update_flags
-);
-
-	assign rd = insn `FIELD_CP_RD;
-	assign writeback = decode.load && rd != `R15;
-	assign update_flags = decode.load && rd == `R15;
-
-	assign decode.crn = insn `FIELD_CP_CRN;
-	assign decode.crm = insn `FIELD_CP_CRM;
-	assign decode.op1 = insn `FIELD_CP_OPCODE;
-	assign decode.op2 = insn `FIELD_CP_OPCODE2;
-	assign decode.load = insn `FIELD_CP_LOAD;
-
-endmodule
diff --git a/rtl/core/decode/coproc_dec.sv b/rtl/core/decode/coproc_dec.sv
new file mode 100644
index 0000000..153cadf
--- /dev/null
+++ b/rtl/core/decode/coproc_dec.sv
@@ -0,0 +1,24 @@
+`include "core/decode/isa.sv"
+`include "core/uarch.sv"
+
+module core_decode_coproc
+(
+	input  word          insn,
+
+	output coproc_decode decode,
+	output reg_num       rd,
+	output logic         writeback,
+	                     update_flags
+);
+
+	assign rd = insn `FIELD_CP_RD;
+	assign writeback = decode.load && rd != `R15;
+	assign update_flags = decode.load && rd == `R15;
+
+	assign decode.crn = insn `FIELD_CP_CRN;
+	assign decode.crm = insn `FIELD_CP_CRM;
+	assign decode.op1 = insn `FIELD_CP_OPCODE;
+	assign decode.op2 = insn `FIELD_CP_OPCODE2;
+	assign decode.load = insn `FIELD_CP_LOAD;
+
+endmodule
diff --git a/rtl/core/decode/data.sv b/rtl/core/decode/data.sv
deleted file mode 100644
index f744972..0000000
--- a/rtl/core/decode/data.sv
+++ /dev/null
@@ -1,65 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_data
-(
-	input  word        insn,
-
-	output data_decode decode,
-	output logic       snd_is_imm,
-	                   snd_shift_by_reg_if_reg,
-	                   writeback,
-	                   conditional,
-	                   update_flags,
-	                   restore_spsr
-);
-
-	alu_op op;
-	reg_num rn, rd;
-	logic uses_rn;
-
-	assign decode.op = op;
-	assign decode.rn = rn;
-	assign decode.rd = rd;
-	assign decode.uses_rn = uses_rn;
-
-	assign rn = insn `FIELD_DATA_RN;
-	assign rd = insn `FIELD_DATA_RD;
-	assign op = insn `FIELD_DATA_OPCODE;
-
-	assign snd_is_imm = insn `FIELD_DATA_IMM;
-	assign snd_shift_by_reg_if_reg = insn `FIELD_DATA_REGSHIFT;
-
-	always_comb begin
-		unique case(op)
-			`ALU_ADC, `ALU_SBC, `ALU_RSC:
-				conditional = 1;
-
-			default:
-				conditional = 0;
-		endcase
-
-		unique case(op)
-			`ALU_CMP, `ALU_CMN, `ALU_TST, `ALU_TEQ:
-				writeback = 0;
-
-			default:
-				writeback = 1;
-		endcase
-
-		unique case(op)
-			`ALU_MOV, `ALU_MVN:
-				uses_rn = 0;
-
-			default:
-				uses_rn = 1;
-		endcase
-
-		update_flags = insn `FIELD_DATA_S;
-		restore_spsr = (rd == `R15) & update_flags;
-
-		if(restore_spsr)
-			update_flags = 0;
-	end
-
-endmodule
diff --git a/rtl/core/decode/data_dec.sv b/rtl/core/decode/data_dec.sv
new file mode 100644
index 0000000..f744972
--- /dev/null
+++ b/rtl/core/decode/data_dec.sv
@@ -0,0 +1,65 @@
+`include "core/decode/isa.sv"
+`include "core/uarch.sv"
+
+module core_decode_data
+(
+	input  word        insn,
+
+	output data_decode decode,
+	output logic       snd_is_imm,
+	                   snd_shift_by_reg_if_reg,
+	                   writeback,
+	                   conditional,
+	                   update_flags,
+	                   restore_spsr
+);
+
+	alu_op op;
+	reg_num rn, rd;
+	logic uses_rn;
+
+	assign decode.op = op;
+	assign decode.rn = rn;
+	assign decode.rd = rd;
+	assign decode.uses_rn = uses_rn;
+
+	assign rn = insn `FIELD_DATA_RN;
+	assign rd = insn `FIELD_DATA_RD;
+	assign op = insn `FIELD_DATA_OPCODE;
+
+	assign snd_is_imm = insn `FIELD_DATA_IMM;
+	assign snd_shift_by_reg_if_reg = insn `FIELD_DATA_REGSHIFT;
+
+	always_comb begin
+		unique case(op)
+			`ALU_ADC, `ALU_SBC, `ALU_RSC:
+				conditional = 1;
+
+			default:
+				conditional = 0;
+		endcase
+
+		unique case(op)
+			`ALU_CMP, `ALU_CMN, `ALU_TST, `ALU_TEQ:
+				writeback = 0;
+
+			default:
+				writeback = 1;
+		endcase
+
+		unique case(op)
+			`ALU_MOV, `ALU_MVN:
+				uses_rn = 0;
+
+			default:
+				uses_rn = 1;
+		endcase
+
+		update_flags = insn `FIELD_DATA_S;
+		restore_spsr = (rd == `R15) & update_flags;
+
+		if(restore_spsr)
+			update_flags = 0;
+	end
+
+endmodule
diff --git a/rtl/core/decode/mul.sv b/rtl/core/decode/mul.sv
deleted file mode 100644
index 114b65b..0000000
--- a/rtl/core/decode/mul.sv
+++ /dev/null
@@ -1,33 +0,0 @@
-`include "core/decode/isa.sv"
-`include "core/uarch.sv"
-
-module core_decode_mul
-(
-	input  word       insn,
-
-	output mul_decode decode,
-	output reg_num    rd,
-	                  rs,
-	                  rm,
-	output logic      update_flags
-);
-
-	logic long_mul;
-	reg_num short_rd, rn;
-
-	assign rd = long_mul ? rn : short_rd;
-	assign rs = insn `FIELD_MUL_RS;
-	assign rm = insn `FIELD_MUL_RM;
-	assign update_flags = insn `FIELD_MUL_S;
-
-	assign decode.add = insn `FIELD_MUL_ACC;
-	assign decode.long_mul = long_mul;
-	assign decode.signed_mul = insn `FIELD_MUL_SIGNED;
-	assign decode.r_add_lo = rn;
-	assign decode.r_add_hi = short_rd;
-
-	assign long_mul = insn `FIELD_MUL_LONG;
-	assign short_rd = insn `FIELD_MUL_RD;
-	assign rn = insn `FIELD_MUL_RN;
-
-endmodule
diff --git a/rtl/core/decode/mul_dec.sv b/rtl/core/decode/mul_dec.sv
new file mode 100644
index 0000000..114b65b
--- /dev/null
+++ b/rtl/core/decode/mul_dec.sv
@@ -0,0 +1,33 @@
+`include "core/decode/isa.sv"
+`include "core/uarch.sv"
+
+module core_decode_mul
+(
+	input  word       insn,
+
+	output mul_decode decode,
+	output reg_num    rd,
+	                  rs,
+	                  rm,
+	output logic      update_flags
+);
+
+	logic long_mul;
+	reg_num short_rd, rn;
+
+	assign rd = long_mul ? rn : short_rd;
+	assign rs = insn `FIELD_MUL_RS;
+	assign rm = insn `FIELD_MUL_RM;
+	assign update_flags = insn `FIELD_MUL_S;
+
+	assign decode.add = insn `FIELD_MUL_ACC;
+	assign decode.long_mul = long_mul;
+	assign decode.signed_mul = insn `FIELD_MUL_SIGNED;
+	assign decode.r_add_lo = rn;
+	assign decode.r_add_hi = short_rd;
+
+	assign long_mul = insn `FIELD_MUL_LONG;
+	assign short_rd = insn `FIELD_MUL_RD;
+	assign rn = insn `FIELD_MUL_RN;
+
+endmodule
diff --git a/rtl/core/regs/map.sv b/rtl/core/regs/map.sv
deleted file mode 100644
index 11085d4..0000000
--- a/rtl/core/regs/map.sv
+++ /dev/null
@@ -1,30 +0,0 @@
-`include "core/uarch.sv"
-
-module core_reg_map
-(
-	input  reg_num   r,
-	input  psr_mode  mode,
-	output logic     is_pc,
-	output reg_index index
-);
-
-	reg_index usr;
-	assign usr = {1'b0, r};
-
-	always_comb begin
-		index = 5'bxxxxx;
-		is_pc = r == `R15;
-
-		if(~is_pc)
-			unique case(mode)
-				`MODE_USR, `MODE_SYS: index = usr;
-				`MODE_FIQ: index = r >=  8 ? usr +  7 : usr;
-				`MODE_IRQ: index = r >= 13 ? usr +  9 : usr;
-				`MODE_UND: index = r >= 13 ? usr + 11 : usr;
-				`MODE_ABT: index = r >= 13 ? usr + 13 : usr;
-				`MODE_SVC: index = r >= 13 ? usr + 15 : usr;
-				default: ;
-			endcase
-	end
-
-endmodule
diff --git a/rtl/core/regs/reg_map.sv b/rtl/core/regs/reg_map.sv
new file mode 100644
index 0000000..11085d4
--- /dev/null
+++ b/rtl/core/regs/reg_map.sv
@@ -0,0 +1,30 @@
+`include "core/uarch.sv"
+
+module core_reg_map
+(
+	input  reg_num   r,
+	input  psr_mode  mode,
+	output logic     is_pc,
+	output reg_index index
+);
+
+	reg_index usr;
+	assign usr = {1'b0, r};
+
+	always_comb begin
+		index = 5'bxxxxx;
+		is_pc = r == `R15;
+
+		if(~is_pc)
+			unique case(mode)
+				`MODE_USR, `MODE_SYS: index = usr;
+				`MODE_FIQ: index = r >=  8 ? usr +  7 : usr;
+				`MODE_IRQ: index = r >= 13 ? usr +  9 : usr;
+				`MODE_UND: index = r >= 13 ? usr + 11 : usr;
+				`MODE_ABT: index = r >= 13 ? usr + 13 : usr;
+				`MODE_SVC: index = r >= 13 ? usr + 15 : usr;
+				default: ;
+			endcase
+	end
+
+endmodule
diff --git a/rtl/top/conspiracion.sv b/rtl/top/conspiracion.sv
index 4d09af8..54c8b95 100644
--- a/rtl/top/conspiracion.sv
+++ b/rtl/top/conspiracion.sv
@@ -2,6 +2,7 @@ module conspiracion
 (
 	input  wire        clk_clk,
 	input  wire        rst_n,
+
 	input  wire        halt,
 `ifdef VERILATOR
 	input  wire        step,
@@ -48,12 +49,7 @@ module conspiracion
 	output wire [7:0]  vga_dac_b
 );
 
-	logic button;
-	logic[3:0] data_be;
-	logic[29:0] addr;
-	logic[31:0] data_rd, data_wr;
-	logic reset_reset_n, cpu_clk, cpu_rst_n, cpu_halt,
-	      ready, write, start, irq;
+	logic button, cpu_halt, reset_reset_n;
 
 `ifdef VERILATOR
 	assign cpu_halt = halt;
@@ -82,38 +78,17 @@ module conspiracion
 	);
 `endif
 
-	arm810 core
-	(
-		.clk(cpu_clk),
-		.rst_n(cpu_rst_n),
-		.halt(cpu_halt),
-		.halted(cpu_halted),
-		.bus_addr(addr),
-		.bus_data_rd(data_rd),
-		.bus_data_wr(data_wr),
-		.bus_data_be(data_be),
-		.bus_ready(ready),
-		.bus_write(write),
-		.bus_start(start),
-`ifndef VERILATOR
-		.step(0),
-		.breakpoint(),
-`endif
-		.*
-	);
-
 	platform plat
 	(
-		.master_0_core_cpu_clk(cpu_clk),
-		.master_0_core_cpu_rst_n(cpu_rst_n),
-		.master_0_core_addr(addr),
-		.master_0_core_data_rd(data_rd),
-		.master_0_core_data_wr(data_wr),
-		.master_0_core_data_be(data_be),
-		.master_0_core_ready(ready),
-		.master_0_core_write(write),
-		.master_0_core_start(start),
-		.master_0_core_irq(irq),
+`ifdef VERILATOR
+		.cpu_0_mp_step(step),
+		.cpu_0_mp_breakpoint(breakpoint),
+`else
+		.cpu_0_mp_step(0),
+		.cpu_0_mp_breakpoint(),
+`endif
+		.cpu_0_mp_cpu_halt(cpu_halt),
+		.cpu_0_mp_cpu_halted(cpu_halted),
 		.pll_0_reset_reset(0), //TODO: reset controller, algún día
 		.pio_0_external_connection_export(pio_leds),
 		.switches_external_connection_export({2'b00, pio_switches}),
diff --git a/tb/platform.sv b/tb/platform.sv
index 570ee4e..a4db086 100644
--- a/tb/platform.sv
+++ b/tb/platform.sv
@@ -2,56 +2,50 @@
 
 module platform
 (
-	input  wire        clk_clk,                          //                       clk.clk
-	input  wire [29:0] master_0_core_addr,               // master_0_core.addr
-	output wire [31:0] master_0_core_data_rd,            //              .data_rd
-	input  wire [31:0] master_0_core_data_wr,            //              .data_wr
-	input  wire [3:0]  master_0_core_data_be,            //              .data_be
-	output wire        master_0_core_ready,              //              .ready
-	input  wire        master_0_core_write,              //              .write
-	input  wire        master_0_core_start,              //              .start
-	output wire        master_0_core_irq,                //                          .irq
-	output wire        master_0_core_cpu_clk,            //                          .cpu_clk
-	output wire        master_0_core_cpu_rst_n,
-	output wire [12:0] memory_mem_a,                     //                    memory.mem_a
-	output wire [2:0]  memory_mem_ba,                    //                          .mem_ba
-	output wire        memory_mem_ck,                    //                          .mem_ck
-	output wire        memory_mem_ck_n,                  //                          .mem_ck_n
-	output wire        memory_mem_cke,                   //                          .mem_cke
-	output wire        memory_mem_cs_n,                  //                          .mem_cs_n
-	output wire        memory_mem_ras_n,                 //                          .mem_ras_n
-	output wire        memory_mem_cas_n,                 //                          .mem_cas_n
-	output wire        memory_mem_we_n,                  //                          .mem_we_n
-	output wire        memory_mem_reset_n,               //                          .mem_reset_n
-	inout  wire [7:0]  memory_mem_dq,                    //                          .mem_dq
-	inout  wire        memory_mem_dqs,                   //                          .mem_dqs
-	inout  wire        memory_mem_dqs_n,                 //                          .mem_dqs_n
-	output wire        memory_mem_odt,                   //                          .mem_odt
-	output wire        memory_mem_dm,                    //                          .mem_dm
-	input  wire        memory_oct_rzqin,                 //                          .oct_rzqin
-	output wire [7:0]  pio_0_external_connection_export, // pio_0_external_connection.export
-	input  wire [7:0]  switches_external_connection_export, // pio_1_external_connection.export
-	input  wire [7:0]  buttons_external_connection_export, // pio_2_external_connection.export
-	input  wire        pll_0_reset_reset,
-	output wire        sys_sdram_pll_0_sdram_clk_clk,
-	input  wire        reset_reset_n /*verilator public*/,//                     reset.reset_n
-	output wire [12:0] vram_wire_addr,                   //                 vram_wire.addr
-	output wire [1:0]  vram_wire_ba,                     //                          .ba
-	output wire        vram_wire_cas_n,                  //                          .cas_n
-	output wire        vram_wire_cke,                    //                          .cke
-	output wire        vram_wire_cs_n,                   //                          .cs_n
-	inout  wire [15:0] vram_wire_dq,                     //                          .dq
-	output wire [1:0]  vram_wire_dqm,                    //                          .dqm
-	output wire        vram_wire_ras_n,                  //                          .ras_n
-	output wire        vram_wire_we_n,                   //                          .we_n
-	output wire        vga_dac_CLK,                      //                   vga_dac.CLK
-	output wire        vga_dac_HS,                       //                          .HS
-	output wire        vga_dac_VS,                       //                          .VS
-	output wire        vga_dac_BLANK,                    //                          .BLANK
-	output wire        vga_dac_SYNC,                     //                          .SYNC
-	output wire [7:0]  vga_dac_R,                        //                          .R
-	output wire [7:0]  vga_dac_G,                        //                          .G
-	output wire [7:0]  vga_dac_B                        //                          .B
+	input  wire [7:0]  buttons_external_connection_export,  //  buttons_external_connection.export
+	input  wire        clk_clk,                             //                          clk.clk
+	input  wire        cpu_0_mp_step,                       //                     cpu_0_mp.step
+	input  wire        cpu_0_mp_cpu_halt,                   //                             .cpu_halt
+	output wire        cpu_0_mp_cpu_halted,                 //                             .cpu_halted
+	output wire        cpu_0_mp_breakpoint,                 //                             .breakpoint
+	output wire [12:0] memory_mem_a,                        //                       memory.mem_a
+	output wire [2:0]  memory_mem_ba,                       //                             .mem_ba
+	output wire        memory_mem_ck,                       //                             .mem_ck
+	output wire        memory_mem_ck_n,                     //                             .mem_ck_n
+	output wire        memory_mem_cke,                      //                             .mem_cke
+	output wire        memory_mem_cs_n,                     //                             .mem_cs_n
+	output wire        memory_mem_ras_n,                    //                             .mem_ras_n
+	output wire        memory_mem_cas_n,                    //                             .mem_cas_n
+	output wire        memory_mem_we_n,                     //                             .mem_we_n
+	output wire        memory_mem_reset_n,                  //                             .mem_reset_n
+	inout  wire [7:0]  memory_mem_dq,                       //                             .mem_dq
+	inout  wire        memory_mem_dqs,                      //                             .mem_dqs
+	inout  wire        memory_mem_dqs_n,                    //                             .mem_dqs_n
+	output wire        memory_mem_odt,                      //                             .mem_odt
+	output wire        memory_mem_dm,                       //                             .mem_dm
+	input  wire        memory_oct_rzqin,                    //                             .oct_rzqin
+	output wire [7:0]  pio_0_external_connection_export,    //    pio_0_external_connection.export
+	input  wire        pll_0_reset_reset,                   //                  pll_0_reset.reset
+	input  wire        reset_reset_n /*verilator public*/,  //                        reset.reset_n
+	input  wire [7:0]  switches_external_connection_export, // switches_external_connection.export
+	output wire        sys_sdram_pll_0_sdram_clk_clk,       //    sys_sdram_pll_0_sdram_clk.clk
+	output wire        vga_dac_CLK,                         //                      vga_dac.CLK
+	output wire        vga_dac_HS,                          //                             .HS
+	output wire        vga_dac_VS,                          //                             .VS
+	output wire        vga_dac_BLANK,                       //                             .BLANK
+	output wire        vga_dac_SYNC,                        //                             .SYNC
+	output wire [7:0]  vga_dac_R,                           //                             .R
+	output wire [7:0]  vga_dac_G,                           //                             .G
+	output wire [7:0]  vga_dac_B,                           //                             .B
+	output wire [12:0] vram_wire_addr,                      //                    vram_wire.addr
+	output wire [1:0]  vram_wire_ba,                        //                             .ba
+	output wire        vram_wire_cas_n,                     //                             .cas_n
+	output wire        vram_wire_cke,                       //                             .cke
+	output wire        vram_wire_cs_n,                      //                             .cs_n
+	inout  wire [15:0] vram_wire_dq,                        //                             .dq
+	output wire [1:0]  vram_wire_dqm,                       //                             .dqm
+	output wire        vram_wire_ras_n,                     //                             .ras_n
+	output wire        vram_wire_we_n                       //                             .we_n
 );
 
 	logic[31:0]  avl_address /*verilator public*/;
@@ -71,20 +65,14 @@ module platform
 	logic       core_avl_waitrequest;
 	logic[3:0]  core_avl_byteenable;
 
-	bus_master master_0
+	core cpu0
 	(
 		.clk(clk_clk),
 		.rst_n(reset_reset_n),
-		.addr(master_0_core_addr),
-		.start(master_0_core_start),
-		.write(master_0_core_write),
-		.ready(master_0_core_ready),
-		.data_rd(master_0_core_data_rd),
-		.data_wr(master_0_core_data_wr),
-		.data_be(master_0_core_data_be),
-		.cpu_clk(master_0_core_cpu_clk),
-		.cpu_rst_n(master_0_core_cpu_rst_n),
-		.irq(master_0_core_irq),
+		.step(cpu_0_mp_step),
+		.breakpoint(cpu_0_mp_breakpoint),
+		.cpu_halt(cpu_0_mp_cpu_halt),
+		.cpu_halted(cpu_0_mp_cpu_halted),
 		.avl_address(core_avl_address),
 		.avl_read(core_avl_read),
 		.avl_write(core_avl_write),
@@ -107,7 +95,7 @@ module platform
 	      data_ready_0, data_ready_1, data_ready_2, data_ready_3,
 	      token_valid_0, token_valid_1, token_valid_2, token_valid_3;
 
-	cache #(.TOKEN_AT_RESET(0)) c0
+	cache #(.TOKEN_AT_RESET(0)) cache0
 	(
 		.clk(clk_clk),
 		.rst_n(reset_reset_n),
@@ -149,7 +137,7 @@ module platform
 		.out_token_valid(token_valid_0)
 	);
 
-	cache #(.TOKEN_AT_RESET(0)) c1
+	cache #(.TOKEN_AT_RESET(0)) cache1
 	(
 		.clk(clk_clk),
 		.rst_n(reset_reset_n),
@@ -191,7 +179,7 @@ module platform
 		.out_token_valid(token_valid_1)
 	);
 
-	cache #(.TOKEN_AT_RESET(0)) c2
+	cache #(.TOKEN_AT_RESET(0)) cache2
 	(
 		.clk(clk_clk),
 		.rst_n(reset_reset_n),
@@ -233,7 +221,7 @@ module platform
 		.out_token_valid(token_valid_2)
 	);
 
-	cache #(.TOKEN_AT_RESET(1)) c3
+	cache #(.TOKEN_AT_RESET(1)) cache3
 	(
 		.clk(clk_clk),
 		.rst_n(reset_reset_n),
diff --git a/tb/top/conspiracion.cpp b/tb/top/conspiracion.cpp
index b243c89..4f0fb3d 100644
--- a/tb/top/conspiracion.cpp
+++ b/tb/top/conspiracion.cpp
@@ -18,6 +18,7 @@
 #include "Vconspiracion_conspiracion.h"
 #include "Vconspiracion_platform.h"
 #include "Vconspiracion_vga_domain.h"
+#include "Vconspiracion_core.h"
 #include "Vconspiracion_core_control.h"
 #include "Vconspiracion_core_control_issue.h"
 #include "Vconspiracion_core_cp15_domain.h"
@@ -386,7 +387,7 @@ int main(int argc, char **argv)
 		std::fclose(img_file);
 	}
 
-	auto &core = *top.conspiracion->core;
+	auto &core = *plat.cpu0->cpu;
 	for(const auto &init : init_regs)
 	{
 		core.regs->a->file[init.index] = init.value;
@@ -473,10 +474,10 @@ int main(int argc, char **argv)
 	};
 
 	Vconspiracion_cache_sram *const caches[] = {
-		plat.c0->sram,
-		plat.c1->sram,
-		plat.c2->sram,
-		plat.c3->sram
+		plat.cache0->sram,
+		plat.cache1->sram,
+		plat.cache2->sram,
+		plat.cache3->sram
 	};
 
 	auto dump_coherent = [&](std::uint32_t addr, std::uint32_t &data)
-- 
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